Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.4.14. HPS Trace Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 31.  HPS Trace PinsYou can select up to 16 trace output pins in the Agilex™ 5 HPS. These pins do not have to be located in the same quadrant.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments
Trace_CLK Trace Clock. Output HPS_IOA_20
HPS_IOB_20
Trace_D0 Trace Data 0. Output HPS_IOA_21
HPS_IOB_21
Trace_D1 Trace Data 1. Output HPS_IOA_22
HPS_IOB_22
Trace_D2 Trace Data 2. Output HPS_IOA_23
HPS_IOB_23
Trace_D3 Trace Data 3. Output HPS_IOA_24
HPS_IOB_24
Trace_D4 Trace Data 4. Output HPS_IOA_19
HPS_IOA_7
HPS_IOB_19
HPS_IOB_7
Trace_D5 Trace Data 5. Output HPS_IOA_18
HPS_IOA_6
HPS_IOB_18
HPS_IOB_6
Trace_D6 Trace Data 6. Output HPS_IOA_17
HPS_IOA_5
HPS_IOB_17
HPS_IOB_5
Trace_D7 Trace Data 7. Output HPS_IOA_16
HPS_IOA_4
HPS_IOB_16
HPS_IOB_4
Trace_D8 Trace Data 8. Output HPS_IOA_15
HPS_IOA_3
HPS_IOB_15
HPS_IOB_3
Trace_D9 Trace Data 9. Output HPS_IOA_14
HPS_IOA_2
HPS_IOB_14
HPS_IOB_2
Trace_D10 Trace Data 10. Output HPS_IOA_13
HPS_IOA_1
HPS_IOB_13
HPS_IOB_1
Trace_D11 Trace Data 11. Output HPS_IOA_12
HPS_IOB_12
Trace_D12 Trace Data 12. Output HPS_IOA_11
HPS_IOB_11
Trace_D13 Trace Data 13. Output HPS_IOA_10
HPS_IOB_10
Trace_D14 Trace Data 14. Output HPS_IOA_9
HPS_IOB_9
Trace_D15 Trace Data 15. Output HPS_IOA_8
HPS_IOB_8
Level Two Title