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1.1. Pins Status for Agilex™ 5 Devices
1.2. Agilex™ 5 FPGA Core Pins
1.3. Agilex™ 5 GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices
1.6. Notes to Agilex™ 5 Pin Connection Guidelines
1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2.1. Clock and PLL Pins
1.2.2. Dedicated Configuration/JTAG Pins
1.2.3. Optional/Dual-Purpose Configuration Pins
1.2.4. Differential I/O Pins
1.2.5. External Memory Interface Pins
1.2.6. Voltage Sensor and Voltage Reference Pins
1.2.7. Remote Temperature Sensing Diode Pins
1.2.8. Reference Pins
1.2.9. HVIO GPIO Pins
1.2.10. HVIO Optional Function Pins
1.2.11. No Connect and DNU Pins
1.2.12. Power Supply Pins
1.2.13. Secure Device Manager (SDM) Pins
1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.4.1. HPS Power Supply Pins
1.4.2. HPS Oscillator Clock Input Pin
1.4.3. HPS JTAG Pins
1.4.4. HPS GPIO Pins
1.4.5. HPS SDMMC Pins
1.4.6. HPS NAND Pins
1.4.7. HPS USB Pins
1.4.8. HPS EMAC Pins
1.4.9. HPS I2C_EMAC and MDIO Pins
1.4.10. HPS I2C Pins
1.4.11. HPS I3C Pins
1.4.12. HPS SPI Pins
1.4.13. HPS UART Pins
1.4.14. HPS Trace Pins
Visible to Intel only — GUID: lix1704882532619
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1.2. Agilex™ 5 FPGA Core Pins
Section Content
Clock and PLL Pins
Dedicated Configuration/JTAG Pins
Optional/Dual-Purpose Configuration Pins
Differential I/O Pins
External Memory Interface Pins
Voltage Sensor and Voltage Reference Pins
Remote Temperature Sensing Diode Pins
Reference Pins
HVIO GPIO Pins
HVIO Optional Function Pins
No Connect and DNU Pins
Power Supply Pins
Secure Device Manager (SDM) Pins
Secure Device Manager (SDM) Optional Signal Pins