Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.4.11. HPS I3C Pins

Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.

There are two I3C controllers (I3C0 and I3C1) for dedicated I3C usage in the Agilex™ 5 HPS.

The I3C protocol requires pull-up resistors to VCCIO_HPS on both the serial data and serial clock signals for them to function correctly. The value of the pull-up resistor varies depending on your board loading. Altera recommends using a 1 kΩ pull-up resistor. Refer to the I3C Controller Design Guidelines and Examples section in the Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs for more information on design guidelines.
Table 28.  HPS I3C
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments (select from one of the groups)
Group 1 Group 2 Group 3 Group 4
I3C0_SDA I3C0 Serial Data. I/O HPS_IOA_11 HPS_IOA_19 HPS_IOB_7 HPS_IOB_17
I3C0_SCL I3C0 Serial Clock. I/O HPS_IOA_12 HPS_IOA_20 HPS_IOB_8 HPS_IOB_18
I3C1_SDA I3C1 Serial Data. I/O HPS_IOA_9 HPS_IOA_17 HPS_IOB_5 HPS_IOB_15
I3C1_SCL I3C1 Serial Clock. I/O HPS_IOA_10 HPS_IOA_18 HPS_IOB_6 HPS_IOB_16
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