Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813266
Date 11/21/2024
Public
Document Table of Contents

1.4.11. HPS I3C Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.

There are two I3C controllers (I3C0 and I3C1) for dedicated I3C usage in the Agilex™ 5 HPS.

The I3C protocol requires pull-up resistors to VCCIO_HPS on both the serial data and serial clock signals for them to function correctly. The value of the pull-up resistor varies depending on your board loading. Altera recommends using a 1 kΩ pull-up resistor. Refer to the I3C Controller Design Guidelines and Examples section in the Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs for more information on design guidelines.
Table 28.  HPS I3C Pins
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments (select from one of the groups)
Group 1 Group 2 Group 3 Group 4
I3C0_SDA I3C0 Serial Data. I/O HPS_IOA_11 HPS_IOA_19 HPS_IOB_7 HPS_IOB_17
I3C0_SCL I3C0 Serial Clock. I/O HPS_IOA_12 HPS_IOA_20 HPS_IOB_8 HPS_IOB_18
I3C0_SDA_PULLUP_EN I3C0 Enable the pull-up resistor.
Note: This pin is only supported in production devices.
Output HPS_IOB_1 HPS_IOB_21
I3C1_SDA I3C1 Serial Data. I/O HPS_IOA_9 HPS_IOA_17 HPS_IOB_5 HPS_IOB_15
I3C1_SCL I3C1 Serial Clock. I/O HPS_IOA_10 HPS_IOA_18 HPS_IOB_6 HPS_IOB_16
I3C1_SDA_PULLUP_EN I3C1 Enable the pull-up resistor.
Note: This pin is only supported in production devices.
Output HPS_IOB_2 HPS_IOB_22