Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.4.7. HPS USB Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 24.  HPS USB PinsThere are two USB controllers (USB0 and USB1) for the Agilex™ 5 HPS. USB0 supports USB 2.0 and USB1 supports USB 3.1. USB 3.1 pins are for ULPI compatibility only.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments
USB0_CLK USB0 Clock. Input HPS_IOA_1
USB0_STP USB0 Stop Data. Output HPS_IOA_2
USB0_DIR USB0 Direction. Input HPS_IOA_3
USB0_DATA0 USB0 Data Bit 0. I/O HPS_IOA_4
USB0_DATA1 USB0 Data Bit 1. I/O HPS_IOA_5
USB0_NXT USB0 Next Data. Input HPS_IOA_6
USB0_DATA2 USB0 Data Bit 2. I/O HPS_IOA_7
USB0_DATA3 USB0 Data Bit 3 I/O HPS_IOA_8
USB0_DATA4 USB0 Data Bit 4. I/O HPS_IOA_9
USB0_DATA5 USB0 Data Bit 5. I/O HPS_IOA_10
USB0_DATA6 USB0 Data Bit 6. I/O HPS_IOA_11
USB0_DATA7 USB0 Data Bit 7. I/O HPS_IOA_12
USB1_CLK USB1 Clock. Input HPS_IOA_13
USB1_STP USB1 Stop Data. Output HPS_IOA_14
USB1_DIR USB1 Direction. Input HPS_IOA_15
USB1_DATA0 USB1 Data Bit 0. I/O HPS_IOA_16
USB1_DATA1 USB1 Data Bit 1. I/O HPS_IOA_17
USB1_NXT USB1 Next Data. Input HPS_IOA_18
USB1_DATA2 USB1 Data Bit 2. I/O HPS_IOA_19
USB1_DATA3 USB1 Data Bit 3. I/O HPS_IOA_20
USB1_DATA4 USB1 Data Bit 4. I/O HPS_IOA_21
USB1_DATA5 USB1 Data Bit 5. I/O HPS_IOA_22
USB1_DATA6 USB1 Data Bit 6. I/O HPS_IOA_23
USB1_DATA7 USB1 Data Bit 7. I/O HPS_IOA_24
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