Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.2.10. HVIO Optional Function Pins

Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Note: Agilex™ 5 FPGA HVIO supports RGMII at 1.8 V.
Table 11.  HVIO Optional Function Pins
Pin Name Pin Functions Pin Description Connection Guidelines
PLLREFCLK[1,2] Input Reference clock input pins for IOPLL.

Provide a single-ended external clock source to this pin.

Connect unused pins as defined in the Quartus® Prime software.

SOURCE_SYNC_CLK[1,2] Input Reference clock input pins to Fabric Core or RGMII interface. These pins can be used as RGMII receive clock when you have RGMII interface connected with the HVIO bank on board.

Provide a single-ended external clock source to this pin when the pin is used as a reference clock.

Connect with RGMII RX_CLK from Ethernet PHY when this pin is used as a RGMII receive clock. You can only use one of the two pins at a time as RGMII_RX_CLK.

Connect unused pins as defined in the Quartus® Prime software.

SYSPLLREFCLK_L1[A,B,C,D][0:1]

SYSPLLREFCLK_R4[A,B,C,D][0:1]

Input Reference clock input pins for system PLL in the GTS transceiver banks. You can also use the system PLL for the core fabric if it is unused by the GTS transceiver.

Provide a single-ended external clock source to this pin.

Connect unused pins as defined in the Quartus® Prime software.

PIN_PERST_N_CVP_L1[A,B,C,D]_[0,1]

PIN_PERST_N_R4[A,B,C,D]_[0,1]

Input

Dual-purpose pin functions as user I/O pin or PCIe* platform reset pin. Two reset pins available for each GTS bank, select either one of the pins. For ES device, if one PERST pin is selected as reset signal for GTS, the unused PERST pin for the same GTS bank must be left floating.

When used as PCIe* platform reset, connect this pin to the system PCIe* nPERST signal. When the pin is low, the transceivers are in reset. When the pin is high, the transceivers are out of reset.

Reset input in PCIe* case. For ES device, if one PERST pin is selected as reset signal for GTS, the unused PERST pin for the same GTS bank must be left floating.

In a PCIe* adapter card implementation, connect this signal from the PCIe* edge connector to each GTS PCIe* reset input pin. You must pull up the 3.3-V PCIe* nPERST signal on the adapter card.

If the pin is assigned to PIN_PERST in the Quartus® Prime IP but GTS is unused, tie to GND.

If VCCIO_HVIO is 1.8-V or 2.5-V, use a level translator to fan out and change the 3.3-V open-drain nPERST signal from the PCIe* connector to this pin of each GTS transceiver that is used on the board.

In case when one reset pin controls multiple PCIe* IPs in bifurcation mode, ensure that this signal is deasserted high after all IPs reference clocks are stable.

TXCLK[1:20] Output Transmit clock. These pins can be used as RGMII transmit clock when you have RGMII interface connected with HVIO bank on board.

Connect unused pins as defined in the Quartus® Prime software.

RXCLK[1:4] Input Reference clock input pins for the fabric core.

Provide a single-ended external clock source to this pin.

Connect unused pins as defined in the Quartus® Prime software.

Data_Ctrl[1:20] Input/Output Data and control signal. These pins can be used as RGMII data and control signal when you have RGMII interface connected with HVIO bank on board.

When these pins are used as RGMII receive data (RXD) or RGMII transmit data (TXD), you must assign the 4 pins for RXD or TXD in groups of 4. For example, [1:4], [5:8], [9:12], [13:16], and [17:20].

Connect unused pins as defined in the Quartus® Prime software.

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