Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.2.3. Optional/Dual-Purpose Configuration Pins

Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Attention: There are pins usage restriction for dual-purpose pins in the Avalon® streaming interface x16 mode, refer to the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs for more details.
Table 4.  Optional/Dual-Purpose Configuration Pins
Pin Name Pin Functions Pin Description Connection Guidelines
AVST_DATA[15:0] I/O, Input

Dual-purpose configuration data input pins.

Use the AVST_DATA[15:0] pins for Avalon® streaming interface x16 mode.

This pin supports the 1.2-V LVCMOS I/O standard only if you are using Avalon® streaming interface x16 configuration scheme.

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

Attention: Access to the I/O pins located in bank 3AT with pin index [91...95] is not allowed for the Avalon® streaming interface x16 configuration scheme. You must leave these pins unconnected. For more information, refer to the device pin mapping files to identify the exact pin location.
If these pins are not used as the dual-purpose pins and they are not used as I/O pins, leave these pins unconnected.
AVST_READY(3ATbank) I/O, Output

Dual-purpose Avalon® streaming interface data ready output pin. Use the AVST_READY(3ATbank) pin for the Avalon® streaming interface x16 configuration schemes.

You cannot use this pin as a user I/O pin if you are using the Avalon® streaming interface x16 configuration scheme.

This pin supports the 1.2-V LVCMOS I/O standard only if you are using Avalon® streaming interface x16 configuration scheme.

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

Connect this pin to the ready signal input of the external configuration controller when configuring using the Avalon® streaming x16 interface.
AVST_CLK(3ATbank) I/O, Input

Dual-purpose Avalon® streaming interface clock input pin. Use the AVST_CLK(3ATbank) for the Avalon® streaming interface x16 configuration schemes.

You can also use his pin as a user I/O pin after configuration.

This pin supports the 1.2-V LVCMOS I/O standard only if you are using Avalon® streaming interface x16 configuration scheme.

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

Connect this pin to the clock signal of the external configuration controller when configuring using the Avalon® streaming x16 interface.

Connect unused pins as defined in the Quartus® Prime software.

AVST_VALID(3ATbank) I/O, Input

Dual-purpose configuration data valid pin. Use the AVST_VALID(3ATbank) pin for the Avalon® streaming interface x16 configuration schemes.

You can also use this pin as a user I/O pin after configuration.

This pin supports the 1.2-V LVCMOS I/O standard only if you are using Avalon® streaming interface x16 configuration scheme.

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

Connect this pin to the data valid signal of the external configuration controller when configuring using the Avalon® streaming x16 interface.

Connect unused pins as defined in the Quartus® Prime software.

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