Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813266
Date 11/21/2024
Public
Document Table of Contents

1.1. Pins Status for Agilex™ 5 Devices

The following descriptors designate the status level currently applicable to the relevant variant:

  • Preliminary: Information in this document is subject to change. Intended for pre-production development, for production designs use with caution.
  • Final: Information in this document is intended for use in production design.
Table 1.  Pins Status for Agilex™ 5 Devices
Tile Status
Core Pins Preliminary
HPS Pins Preliminary
GTS Transceiver Pins Preliminary
HVIO Pins Preliminary