Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 10/17/2024
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Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.4.1. HPS Power Supply Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 18.  HPS Power Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCL_HPS Power VCCL_HPS supplies power to the HPS DSU and periphery circuitry.

For the range of the VCCL_HPS power supply voltage, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet . Altera recommends you share VCCL_HPS with VCC together.

If you do not intend to utilize the HPS in the Agilex™ 5 device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS floating or connected to GND.

VCCL_HPS_CORE0_CORE1 Power Supply power to HPS A55 Core 0 and Core 1.

For the range of the VCCL_HPS_CORE0_CORE1 power supply voltage, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

VCCL_HPS_CORE0_CORE1 must be sourced from the same regulator with VCCL_HPS. Altera recommends you share this power with VCC together.

You have the option to connect this pin to GND if you do not intend to use the Cortex* -A55 cores.

VCCL_HPS_CORE2 Power Supply power to the HPS A76 Core 2.

For the range of the VCCL_HPS_CORE2 power supply voltage, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

VCCL_HPS_CORE2 must be sourced from the same regulator with VCCL_HPS. Altera recommends you share this power with VCC together.

You have the option to connect this pin to GND if you do not intend to use the Cortex* -A76 core 2.

VCCL_HPS_CORE3 Power Supply power to the HPS A76 Core 3.

For the range of the VCCL_HPS_CORE3 power supply voltage, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

VCCL_HPS_CORE3 must be sourced from the same regulator with VCCL_HPS. Altera recommends you share this power with VCC together.

You have the option to connect this pin to GND if you do not intend to use the Cortex* -A76 core 3.

VCCIO_HPS Power The HPS dedicated I/Os support 1.8-V voltage level.

Connect these pins to 1.8-V power supply. You have the option to source VCCIO_HPS pins from the same regulator as VCCPT.

If you do not intend to utilize the HPS in the Agilex™ 5 device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS floating or connected to GND.

VCCPLL1_HPS Power Supply analog power to the main HPS PLLs.

Connect these pins to a 1.8-V power supply. You have the option to share VCCPLL1_HPS with the same regulator as VCCPLL_SDM.

If you do not intend to utilize the HPS in the Agilex™ 5 device, you must still provide power to the HPS power supply. Do not leave the VCCPLL1_HPS floating or connected to GND.

VCCPLL2_HPS Power Supply analog power to the peripheral HPS PLLs.

Connect these pins to a 1.8-V power supply. You have the option to share VCCPLL2_HPS with the same regulator as VCCPLL_SDM.

If you do not intend to utilize the HPS in the Agilex™ 5 device, you must still provide power to the HPS power supply. Do not leave the VCCPLL2_HPS floating or connected to GND.

VCCPLLDIG1_HPS Power Digital power supply of the main HPS PLLs.

Connect this to the VCCL_HPS with proper isolation filtering.

If you do not intend to utilize the HPS in the Agilex™ 5 device, you must still provide power to the HPS power supply. Do not leave the VCCPLLDIG1_HPS floating or connected to GND.

VCCPLLDIG2_HPS Power Digital power supply of the peripheral HPS PLLs.

Connect this to the VCCL_HPS with proper isolation filtering.

If you do not intend to utilize the HPS in the Agilex™ 5 device, you must still provide power to the HPS power supply. Do not leave the VCCPLLDIG2_HPS floating or connected to GND.

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