Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.6. Notes to Agilex™ 5 Pin Connection Guidelines

Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.

Altera provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.

  1. Use the Intel® FPGA Power and Thermal Calculator to determine the preliminary current requirements for VCC and other power supplies. Use the Quartus® Prime Power Analyzer for the most accurate current requirements for this and other power supplies.
  2. Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via. VCC must not share breakout vias.
  3. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express (PCIe) protocol requires the AC-coupling capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
  4. Low Noise Switching Regulator—defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800 kHz and 1 MHz and has fast transient response. The switching frequency range is not an Altera requirement.
  5. There are no dedicated PR_REQUEST, PR_ERROR, and PR_DONE pins. If required, you can use user I/O pins for these functions.
  6. The device orientation is died view (bottom of chip view).
  7. All I/O pins in a HSIO bank are configured as tri-stated with weak pull-up enabled during device power up (after VCCIO_PIO is fully powered up) and device configuration. During device power down, the I/O pin signals are measured between GND to VCCIO_PIO voltage level when VCCIO_PIO is powering down. All valid data transactions should start after the device enters user mode.
  8. All I/O pins in a HVIO bank are configured as tri-stated during device power up (after VCCIO_HVIO is fully powered up) and device configuration. During device power down, the I/O pin signals are measured between GND to VCCIO_HVIO voltage level when the VCCIO_HVIO are powering down. All valid data transactions should start after the device enters user mode.
  9. All dedicated configuration/JTAG, SDM, and SDM optional signal pins are in the undetermined state during device power up and power down. All I/O in the SDM pins are configured as defined in the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs and LVDS SERDES User Guide: Agilex™ 5 FPGAs and SoCs during device configuration.
  10. All I/O pins in HPS banks are in the undetermined state during device power up and power down. All I/Os in the HPS pins are configured as the Schmitt trigger input with 20-kΩ weak pull-up enabled after the device is powered up and during HPS or device configuration. All HPS data transaction should start after the device is fully powered up.
  11. Input signals of all HSIO, HPS, and SDM I/O pins at any point during power up and power down should not exceed the I/O buffer power supply rail of the bank where the I/O pin resides in. If you use a pin in a GPIO bank with 1.3-V VCCIO_PIO, the pin voltage must not exceed the VCCIO_PIO rail or 1.2 V, whichever is lower.
  12. Input signals of all HVIO pins at any point during power up and power down should not exceed the I/O buffer power supply rail of the bank where I/O resides in.
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