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1.1. Pins Status for Agilex™ 5 Devices
1.2. Agilex™ 5 FPGA Core Pins
1.3. Agilex™ 5 GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices
1.6. Notes to Agilex™ 5 Pin Connection Guidelines
1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2.1. Clock and PLL Pins
1.2.2. Dedicated Configuration/JTAG Pins
1.2.3. Optional/Dual-Purpose Configuration Pins
1.2.4. Differential I/O Pins
1.2.5. External Memory Interface Pins
1.2.6. Voltage Sensor and Voltage Reference Pins
1.2.7. Remote Temperature Sensing Diode Pins
1.2.8. Reference Pins
1.2.9. HVIO GPIO Pins
1.2.10. HVIO Optional Function Pins
1.2.11. No Connect and DNU Pins
1.2.12. Power Supply Pins
1.2.13. Secure Device Manager (SDM) Pins
1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.4.1. HPS Power Supply Pins
1.4.2. HPS Oscillator Clock Input Pin
1.4.3. HPS JTAG Pins
1.4.4. HPS GPIO Pins
1.4.5. HPS SDMMC Pins
1.4.6. HPS NAND Pins
1.4.7. HPS USB Pins
1.4.8. HPS EMAC Pins
1.4.9. HPS I2C_EMAC and MDIO Pins
1.4.10. HPS I2C Pins
1.4.11. HPS I3C Pins
1.4.12. HPS SPI Pins
1.4.13. HPS UART Pins
1.4.14. HPS Trace Pins
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1.4.6. HPS NAND Pins
Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
HPS Pin Functions | Pin Description and Connection Guidelines | Pin Type | Valid Assignments (select from one of the groups) | |
---|---|---|---|---|
Group 1 | Group 2 | |||
NAND_ADQ0 | NAND Data Bit 0. | I/O | HPS_IOA_1 | HPS_IOB_1 |
NAND_ADQ1 | NAND Data Bit 1. | I/O | HPS_IOA_2 | HPS_IOB_2 |
NAND_WE_N | NAND Write Enable. This is an active-low signal. |
Output | HPS_IOA_3 | HPS_IOB_3 |
NAND_RE_N | NAND Read Enable. This is an active-low signal. |
Output | HPS_IOA_4 | HPS_IOB_4 |
NAND_WP_N | NAND Write Protect. This is an active-low signal. |
Output | HPS_IOA_5 | HPS_IOB_5 |
NAND_ADQ2 | NAND Data Bit 2 | I/O | HPS_IOA_6 | HPS_IOB_6 |
NAND_ADQ3 | NAND Data Bit 3 | I/O | HPS_IOA_7 | HPS_IOB_7 |
NAND_CLE | NAND Command Latch Enable. This is an active-high signal. |
Output | HPS_IOA_8 | HPS_IOB_8 |
NAND_ADQ4 | NAND Data Bit 4. | I/O | HPS_IOA_9 | HPS_IOB_9 |
NAND_ADQ5 | NAND Data Bit 5. | I/O | HPS_IOA_10 | HPS_IOB_10 |
NAND_ADQ6 | NAND Data Bit 6. | I/O | HPS_IOA_11 | HPS_IOB_11 |
NAND_ADQ7 | NAND Data Bit 7. | I/O | HPS_IOA_12 | HPS_IOB_12 |
NAND_ALE | NAND Address Latch Enable. This is an active-high signal. |
Output | HPS_IOA_13 | HPS_IOB_13 |
NAND_RB_N | NAND Ready/Busy. Connect this pin through a pull-up resistor to VCCIO_HPS. For more information of the pull-up resistor value, refer to the NAND flash specification. |
Input | HPS_IOA_14 | HPS_IOB_14 |
NAND_CE_N | NAND Chip Enable. This is an active-low signal. |
Output | HPS_IOA_15 | HPS_IOB_15 |
NAND_DQS | NAND signal to indicate data valid window. | Output | HPS_IOA_16 | HPS_IOB_16 |
NAND_ADQ8 | NAND Data Bit 8. | I/O | HPS_IOA_17 | HPS_IOB_17 |
NAND_ADQ9 | NAND Data Bit 9. | I/O | HPS_IOA_18 | HPS_IOB_18 |
NAND_ADQ10 | NAND Data Bit 10. | I/O | HPS_IOA_19 | HPS_IOB_19 |
NAND_ADQ11 | NAND Data Bit 11. | I/O | HPS_IOA_20 | HPS_IOB_20 |
NAND_ADQ12 | NAND Data Bit 12. | I/O | HPS_IOA_21 | HPS_IOB_21 |
NAND_ADQ13 | NAND Data Bit 13. | I/O | HPS_IOA_22 | HPS_IOB_22 |
NAND_ADQ14 | NAND Data Bit 14. | I/O | HPS_IOA_23 | HPS_IOB_23 |
NAND_ADQ15 | NAND Data Bit 15. | I/O | HPS_IOA_24 | HPS_IOB_24 |