Visible to Intel only — GUID: eab1705040794962
Ixiasoft
1.1. Pins Status for Agilex™ 5 Devices
1.2. Agilex™ 5 FPGA Core Pins
1.3. Agilex™ 5 GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices
1.6. Notes to Agilex™ 5 Pin Connection Guidelines
1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2.1. Clock and PLL Pins
1.2.2. Dedicated Configuration/JTAG Pins
1.2.3. Optional/Dual-Purpose Configuration Pins
1.2.4. Differential I/O Pins
1.2.5. External Memory Interface Pins
1.2.6. Voltage Sensor and Voltage Reference Pins
1.2.7. Remote Temperature Sensing Diode Pins
1.2.8. Reference Pins
1.2.9. HVIO GPIO Pins
1.2.10. HVIO Optional Function Pins
1.2.11. No Connect and DNU Pins
1.2.12. Power Supply Pins
1.2.13. Secure Device Manager (SDM) Pins
1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.4.1. HPS Power Supply Pins
1.4.2. HPS Oscillator Clock Input Pin
1.4.3. HPS JTAG Pins
1.4.4. HPS GPIO Pins
1.4.5. HPS SDMMC Pins
1.4.6. HPS NAND Pins
1.4.7. HPS USB Pins
1.4.8. HPS EMAC Pins
1.4.9. HPS I2C_EMAC and MDIO Pins
1.4.10. HPS I2C Pins
1.4.11. HPS I3C Pins
1.4.12. HPS SPI Pins
1.4.13. HPS UART Pins
1.4.14. HPS Trace Pins
Visible to Intel only — GUID: eab1705040794962
Ixiasoft
1.4.12. HPS SPI Pins
Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments (select from one of the group) | ||
---|---|---|---|---|---|
Group 1 | Group 2 | Group 3 | |||
SPIM0_CLK | SPIM0 Clock. | Output | HPS_IOA_5 | HPS_IOB_21 | HPS_IOB_21 |
SPIM0_MOSI | SPIM0 Master Out Slave In. | Output | HPS_IOA_6 | HPS_IOB_22 | HPS_IOB_22 |
SPIM0_MISO | SPIM0 Master In Slave Out. | Input | HPS_IOA_7 | HPS_IOB_19 | HPS_IOB_23 |
SPIM0_SS0_N | SPIM0 Slave Select 0. This is an active-low signal. |
Output | HPS_IOA_8 | HPS_IOB_20 | HPS_IOB_24 |
SPIM0_SS1_N | SPIM0 Slave Select 1. This is an active-low signal. |
Output | HPS_IOA_1 | HPS_IOB_18 | HPS_IOB_18 |
SPIM1_CLK | SPIM1 Clock. | Output | HPS_IOA_9 | HPS_IOA_21 | HPS_IOB_1 |
SPIM1_MOSI | SPIM1 Master Out Slave In. | Output | HPS_IOA_10 | HPS_IOA_22 | HPS_IOB_2 |
SPIM1_MISO | SPIM1 Master In Slave Out. | Input | HPS_IOA_11 | HPS_IOA_23 | HPS_IOB_3 |
SPIM1_SS0_N | SPIM1 Slave Select 0. This is an active-low signal. |
Output | HPS_IOA_12 | HPS_IOA_24 | HPS_IOB_4 |
SPIM1_SS1_N | SPIM1 Slave Select 1. This is an active-low signal. |
Output | HPS_IOA_2 | HPS_IOA_20 | HPS_IOB_5 |
SPIS0_CLK | SPIS0 Clock. | Input | HPS_IOA_1 | HPS_IOA_21 | HPS_IOB_9 |
SPIS0_MOSI | SPIS0 Master Out Slave In. | Input | HPS_IOA_2 | HPS_IOA_22 | HPS_IOB_10 |
SPIS0_MISO | SPIS0 Master In Slave Out. | Output | HPS_IOA_4 | HPS_IOA_24 | HPS_IOB_12 |
SPIS0_SS0_N | SPIS0 Slave Select 0. This is an active-low signal. |
Input | HPS_IOA_3 | HPS_IOA_23 | HPS_IOB_11 |
SPIS1_CLK | SPIS1 Clock. | Input | HPS_IOA_9 | HPS_IOB_5 | HPS_IOB_21 |
SPIS1_MOSI | SPIS1 Master Out Slave In. | Input | HPS_IOA_10 | HPS_IOB_6 | HPS_IOB_22 |
SPIS1_MISO | SPIS1 Master In Slave Out. | Output | HPS_IOA_12 | HPS_IOB_8 | HPS_IOB_24 |
SPIS1_SS0_N | SPIS1 Slave Select 0. This is an active-low signal. |
Input | HPS_IOA_11 | HPS_IOB_7 | HPS_IOB_23 |