Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.3.2. GTS Transceiver Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 17.  GTS Transceiver Pins
Pin Name Pin Functions Pin Description Connection Guidelines
RCOMP_GTS[L1,R4][A,B,C,D]_P Input External biasing resistor for GTS.

Connect each RCOMP_GTS[L1,R4][A,B,C,D]_P pin with a 499-Ω resistor (± 0.1%) to the RCOMP_GTS[L1,R4][A,B,C,D]_N pin.

In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals.

Leave these floating if the entire side of the GTS transceiver banks are unused.

RCOMP_GTS[L1,R4][A,B,C,D]_N
REFCLK_GTS[L1,R4][A,B,C,D]_CH1p Input/Output

Local reference clock pins for GTS transceiver banks. This pin can be used as an input reference clock pin, or as an output for the CDR recovered clock.

This pin is input-only for banks with the CDRCLKOUT pin.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled. Clock driver must be compatible with input requirement in DC coupling case.

Tie to GND if these pins are not used.

REFCLK_GTS[L1,R4][A,B,C,D]_CH1n
CDRCLKOUT_GTS[L1,R4][A,B,C]_CH2p Output

CDR recovered clock output pins for GTS transceiver banks. This pin is only available in certain banks depending on the device variant.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled.

Leave unused pins floating.
CDRCLKOUT_GTS[L1,R4][A,B,C]_CH2n
REFCLK_GTS[L1,R4][A,B,C,D]_RX_P Input

Regional reference clock input pins for GTS transceiver banks.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled. Clock driver must be compatible with input requirement in DC coupling case.

Tie to GND if these pins are not used.

REFCLK_GTS[L1,R4][A,B,C,D]_RX_N
GTS[L1,R4][A,B,C,D]_RX_CH[0,1,2,3]p Input

GTS transceiver input pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled.

Tie to GND if these pins are not used.

GTS[L1,R4][A,B,C,D]_RX_CH[0,1,2,3]n
GTS[L1,R4][A,B,C,D]_TX_CH[0,1,2,3]p Output

GTS transceiver output pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled.

Leave unused pins floating.
GTS[L1,R4][A,B,C,D]_TX_CH[0,1,2,3]n
APROBE_GTS[L1,R4][A,B,C,D]_CH[0,1,2,3] — — Leave these pins floating.
APROBE2_GTS[L1,R4][A,B,C,D] — — Leave these pins floating.
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