1.2.14. Secure Device Manager (SDM) Optional Signal Pins
Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
| Signal Name | Signal Description | Connection Guidelines | Configuration Schemes | ||
|---|---|---|---|---|---|
| ASx4 | AVSTx8 | AVSTx16 | |||
| PWRMGT_SCL | PMBus Power Management Clock. This pin is used as the clock pin for the PMBus interface. |
This pin requires a pull-up resistor to the 1.8-V VCCIO_SDM supply. Altera recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8 V. Connect this pin to the PMBus clock pin of your regulator. When a –V or –E power option device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements. You can do this by connecting the PWRMGT_SCL and PWRMGT_SDA signals to the VCC voltage regulator for the PMBus master mode and the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals to the external master controller for the PMBus slave mode.
Note: Altera recommends holding the voltage level translators disabled by default to ensure that bus contention, excessive currents, or oscillations do not occur during FPGA rails ramp up or down.
|
SDM_IO0 SDM_IO14 |
SDM_IO0 |
SDM_IO0 SDM_IO14 |
| PWRMGT_SDA | PMBus Power Management Clock. This pin is used as the clock pin for the PMBus interface. |
This pin requires a pull-up resistor to the 1.8-V VCCIO_SDM supply. Altera recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8 V. Connect this pin to the PMBus data pin of your regulator. When a Agilex™ 5 –V or –E power option device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements. You can do this by connecting the PWRMGT_SCL and PWRMGT_SDA signals to the VCC voltage regulator for the PMBus master mode and the PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals to the external master controller for the PMBus slave mode.
Note: Altera recommends holding the voltage level translators disabled by default to ensure that bus contention, excessive currents, or oscillations do not occur during FPGA rails ramp up or down.
|
SDM_IO11 SDM_IO12 SDM_IO16 |
SDM_IO12 SDM_IO16 |
SDM_IO11 SDM_IO12 SDM_IO16 |
| PWRMGT_ALERT | PMBus Power Management Alert. This pin is used as the ALERT function for the PMBus interface when the Agilex™ 5 –V or –E power option device is the PMBus slave. |
This pin requires a pull-up resistor to the 1.8-V VCCIO_SDM supply. Altera recommends a pull-up value of 5.1-kΩ to 10-kΩ depending on the loading of this pin. Use the voltage level translators when interfacing to the PMBus interfaces requiring voltages other than 1.8 V. You must connect this pin to the PMBus ALERT pin of the external master controller. When using the SmartVID feature with the Agilex™ 5 –V or –E power option device as a PMBus slave, you must connect the PWRMGT_ALERT signal along with the PWRMGT_SCL and PWRMGT_SDA signals to the PMBus master device to complete the SmartVID power management interface. The PMBus master device reads the VID codes from the Agilex™ 5 slave and programs the voltage regulator to output the correct VID voltage.
Note: Altera recommends holding the voltage level translators disabled by default to ensure that bus contention, excessive currents, or oscillations do not occur during FPGA rails ramp up or down.
|
SDM_IO0 SDM_IO12 |
SDM_IO0 SDM_IO9 SDM_IO12 |
SDM_IO0 SDM_IO9 SDM_IO12 |
| CONF_DONE | The CONF_DONE pin indicates all configuration data has been received. |
By default, Altera recommends using the SDM_IO16 pin to implement the CONF_DONE function. If SDM_IO16 is unavailable, the CONF_DONE function can also be implemented using any unused SDM_IO pins. Except for SDM_IO0 and SDM_IO16, other SDM_IO pins are required to connect to an external 4.7-kΩ pull-down resistor for the CONF_DONE signal. Connect the CONF_DONE pin to the external configuration controller when configuring using the Avalon® streaming interface. You have an option to monitor this signal with an external component if you are using the active serial (AS) x4 configuration scheme. |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO16 |
SDM_IO0 SDM_IO5 SDM_IO12 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO6 SDM_IO7 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
| INIT_DONE | The INIT_DONE pin indicates the device has enter user mode upon completion of configuration. When used for this purpose, this pin must be enabled by the Quartus® Prime software. When the INIT_DONE function is enabled, this pin drives high when configuration is completed and the device goes into user mode. |
Altera recommends you to use SDM_IO0 or SDM_IO16 to implement the INIT_DONE function when available as it has an internal weak pull-down for the correct function of INIT_DONE during power up. If SDM_IO0 and SDM_IO16 are unavailable, SDM_IO5 can also be used for the INIT_DONE function when the configuration mode is set to Avalon® streaming x8 or Avalon® streaming x32 as these modes require an external 4.7–kΩ pull-down resistor. If SDM_IO0, SDM_IO5, and SDM_IO16 are unavailable, the INIT_DONE function can also be implemented using any unused SDM_IO pins provided that an external 4.7–kΩ pull-down resistor is provided for the INIT_DONE signal. You must enable the INIT_DONE when operating in the SmartVID slave mode. For more information, refer to Power Management User Guide: Agilex™ 5 FPGAs and SoCs . |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO16 |
SDM_IO0 SDM_IO5 SDM_IO12 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO6 SDM_IO7 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
| CvP_CONFDONE | The CvP_CONFDONE pin indicates the device has received the complete bitstream during configuration via protocol (CvP) core image configuration. When used for this purpose, enable this pin using the Quartus® Prime software. |
Connect this output pin to an external logic device that monitors the CvP operation. The VCCIO_SDM power supply must meet the input voltage specification of the receiving side. |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO16 |
SDM_IO0 SDM_IO5 SDM_IO7 SDM_IO9 SDM_IO12 SDM_IO16 |
— |
| SEU_ERROR | The SEU_ERROR pin drives high to indicate there is an SEU error message inside the SEU error queue. This pin stays high whenever the error message queue contains one or more error messages. The SEU_ERROR signal goes low only when the SEU error message queue is empty. When used for this purpose, enable this pin using the Quartus® Prime software. |
Connect this output pin to an external logic device that monitors the SEU event. |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO16 |
SDM_IO0 SDM_IO5 SDM_IO7 SDM_IO9 SDM_IO12 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
| HPS_COLD_nRESET | This is an active low, bidirectional pin. By default, this pin acts as an input pin to the SDM. When asserted externally, this pin generates interrupt to the SDM. The SDM then initiates a cold reset procedure to the HPS and its peripherals. If the cold reset is generated from internal sources (for example, the HPS EL3 software), the SDM switches this pin to output and drives a pulse to indicate reset. Once the cold reset procedure is complete, this pin switches back to input. |
Connect this pin through a 1–10-kΩ pull up to the VCCIO_SDM supply. If using the HPS_COLD_nRESET functionality of this pin, connect this pin to an external logic device that manages the HPS Cold Reset behavior. External devices must release this signal and allow the pin to float high when not driving it low. Do not connect this pin to the reset input of any connected quad serial peripheral interface (quad SPI) devices. If you do not intend to utilize the HPS, do not use this optional SDM signal on this pin. |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO16 |
SDM_IO0 SDM_IO5 SDM_IO7 SDM_IO9 SDM_IO12 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |
| Direct to Factory Image | Direct to factory input pin. When using the remote system upgrade feature, this optional pin allows you to choose between factory or application image. Driving logic high into this pin instructs the device to load factory image, while driving logic low into this pin instructs the device to load the application image. |
Connect this input pin to an external logic device that manages the remote system upgrade of the device. By default, the external logic should provide logic low to this pin so that the application image becomes the default image of the device, and only switch to factory image if required. |
SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO16 |
— | — |
| nCATTRIP | The catastrophic trip signal, nCATTRIP, is an optional signal that you can assign to any unused SDM_IO pin. If enabled, the nCATTRIP signal always stays high and drives low when the core temperature is greater than the temperature threshold point that you set for your design. When the signal drives low, you must immediately power down the FPGA to avoid permanent damage to the device. | Connect this output pin to an external device that monitors the nCATTRIP event. | SDM_IO0 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO16 |
SDM_IO0 SDM_IO5 SDM_IO7 SDM_IO9 SDM_IO12 SDM_IO16 |
SDM_IO0 SDM_IO1 SDM_IO2 SDM_IO3 SDM_IO4 SDM_IO5 SDM_IO6 SDM_IO7 SDM_IO9 SDM_IO10 SDM_IO11 SDM_IO12 SDM_IO13 SDM_IO14 SDM_IO15 SDM_IO16 |