Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP User Guide

ID 789389
Date 7/15/2024
Public
Document Table of Contents

7.2.10. Offset 0x0038 Read Access Control Policy (Lower DWORD)

Bits Access Type Default Description
31:0 RW 0

Read Access Control Policy (RACCTLP).

Bit wise register where each bit represent the 6-bit SAI Index that mapped to a particular 8-bit SAI value or values.

A value ‘1’ in this register bit means that a cycle with SAI value that match the mapped 8-bit SAI value or values has read access to the configuration register space or memory-mapped IO register space.

A value ‘0’ in this register bit means that a cycle with SAI value that match the mapped 8-bit SAI value or values does not have read access.

The default value is determined by input port SAI_RACCTLP_XXXX[63:0].