Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP User Guide

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ID 789389
Date 7/15/2024
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Document Table of Contents
Document Table of Contents x
1. About the Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP 2. Introduction to Memory Subsystem IP 3. Memory Subsystem IP Architecture and Feature Description 4. Memory Subsystem Features 5. Memory Subsystem Interfaces and Signals 6. Memory Subsystem User Operations 7. Memory Subsystem Register Descriptions 8. Parameterizing the Memory Subsystem IP 9. Simulating a Design Example 10. Document Revision History for Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP User Guide
1. About the Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP x
1.1. Release Information
2. Introduction to Memory Subsystem IP x
2.1. Memory Subsystem Features 2.2. Getting Started with the Memory Subsystem IP 2.3. Memory Subsystem Resource Utilization
3. Memory Subsystem IP Architecture and Feature Description x
3.1. Memory-Specific Adaptor 3.2. Memory Subsystem Lookup Core IPs
3.1. Memory-Specific Adaptor x
3.1.1. Memory Subsystem Functional Description
3.1.1. Memory Subsystem Functional Description x
3.1.1.1. Write Data Replication 3.1.1.2. Bank Spreading 3.1.1.3. Memory Subsystem IP Scheduler 3.1.1.4. Memory Subsystem Auto-Precharge
3.2. Memory Subsystem Lookup Core IPs x
3.2.1. Memory Subsystem BCAM 3.2.2. Memory Subsystem TCAM 3.2.3. Memory Subsystem Multi-Bin Lookup (MBL)
3.2.1. Memory Subsystem BCAM x
3.2.1.1. Memory Subsystem BCAM Operations
3.2.2. Memory Subsystem TCAM x
3.2.2.1. Memory Subsystem TCAM Core Table 3.2.2.2. Memory Subsystem TCAM Operations
3.2.3. Memory Subsystem Multi-Bin Lookup (MBL) x
3.2.3.1. Memory Subsystem Multi-Bin Lookup (MBL) Functional Description 3.2.3.2. Pointers 3.2.3.3. Memory Subsystem MBL Operations 3.2.3.4. Row Collisions 3.2.3.5. Signature Collisions 3.2.3.6. Optimization Features
4. Memory Subsystem Features x
4.1. Memory-Specific Adaptor 4.2. External Memory Interface 4.3. Lookup IPs
4.2. External Memory Interface x
4.2.1. External Memory Interfaces IP Parameters Tab
4.3. Lookup IPs x
4.3.1. TCAM 4.3.2. BCAM 4.3.3. MBL
5. Memory Subsystem Interfaces and Signals x
5.1. AXI Memory Mapped (AXI-MM) Interface 5.2. AXI-Lite Interface 5.3. Lookup IPs 5.4. Request/Acknowledge and Reset Signals 5.5. Clock Signals
5.3. Lookup IPs x
5.3.1. TCAM AXI-ST Request Interface 5.3.2. TCAM AXI-ST Response Interface 5.3.3. TCAM AXI-Lite Interface 5.3.4. BCAM AXI-ST Request Interface 5.3.5. BCAM AXI-ST Response Interface 5.3.6. BCAM AXI-Lite Interface 5.3.7. MBL AXI-ST Request Interface 5.3.8. MBL AXI-ST Response Interface 5.3.9. MBL AXI-Lite Interface
6. Memory Subsystem User Operations x
6.1. Memory Specific Adaptor 6.2. Performing TCAM Operations 6.3. Performing BCAM Operations 6.4. Performing MBL Operations
6.2. Performing TCAM Operations x
6.2.1. TCAM Flush Operations 6.2.2. TCAM Insert Operations 6.2.3. TCAM Delete by Entry ID Operations 6.2.4. TCAM Delete by Key Operations 6.2.5. TCAM Lookup Operations through the AXI-Lite Interface 6.2.6. TCAM Lookup Operations through the AXI-ST Interface
6.3. Performing BCAM Operations x
6.3.1. BCAM Flush Operations 6.3.2. BCAM Insert Operations 6.3.3. BCAM Modify Operations 6.3.4. BCAM Delete Operations 6.3.5. BCAM Lookup Operations through the AXI-Lite Interface 6.3.6. BCAM Lookup Operations through the AXI ST Interface
6.4. Performing MBL Operations x
6.4.1. MBL Flush Operation 6.4.2. MBL Insert Key Operation 6.4.3. MBL Delete Key Operation 6.4.4. MBL Lookup Operation Using Key 6.4.5. MBL Modify Operation 6.4.6. MBL Modify Result Using Handle Operation 6.4.7. MBL Delete Key Using Handle Operation 6.4.8. MBL Lookup Using Handle Operation 6.4.9. MBL Insert Key if Not Present or Modify Result if Present Operation 6.4.10. MBL Get Handle Operation
7. Memory Subsystem Register Descriptions x
7.1. Device Feature List 7.2. Memory Base Sub-System Global CSR 7.3. BCAM Registers 7.4. TCAM Registers 7.5. MBL Registers
7.1. Device Feature List x
7.1.1. Device Feature Header
7.2. Memory Base Sub-System Global CSR x
7.2.1. Offset 0x0000 Version 7.2.2. Offset 0x0004 Feature List 7.2.3. Offset 0x0010 Memory Interfaces 0-7 7.2.4. Offset 0x0014 Memory Interfaces 8-15 7.2.5. Offset 0x0018 Memory Interfaces 16-23 7.2.6. Offset 0x001C Memory Interfaces 24-31 7.2.7. Offset 0x0020 Scratch Pad 7.2.8. Offset 0x0030 Control Policy (Lower DWORD) 7.2.9. Offset 0x0034 Control Policy (Upper DWORD) 7.2.10. Offset 0x0038 Read Access Control Policy (Lower DWORD) 7.2.11. Offset 0x003C Read Access Control Policy (Upper DWORD) 7.2.12. Offset 0x0040 Write Access Control Policy (Lower DWORD) 7.2.13. Offset 0x0044 Write Access Control Policy (Upper DWORD) 7.2.14. Offset 0x0050 Memory Status Bitmask 0 7.2.15. Offset 0x0054 Memory Status Bitmask 1 7.2.16. Offset 0x0058 Memory Ready Status 0 7.2.17. Offset 0x005C Memory Ready Status 1 7.2.18. Offset 0x0060 Memory Error Status 0 7.2.19. Offset 0x0064 Memory Error Status 1
7.3. BCAM Registers x
7.3.1. Device Feature Header (DFH)-Specific Registers 7.3.2. General BCAM Registers
7.3.1. Device Feature Header (DFH)-Specific Registers x
7.3.1.1. Field Names and Values
7.3.2. General BCAM Registers x
7.3.2.1. Version 7.3.2.2. Feature List 7.3.2.3. Interface Attribute Parameters 7.3.2.4. Interface Attribute Parameters 1 7.3.2.5. Scratch Pad 7.3.2.6. General Control (GEN_CTRL) 7.3.2.7. Management Control (MGMT_CTRL) 7.3.2.8. Hash function_0 seed 7.3.2.9. Hash function_1 seed 7.3.2.10. Hash function_2 seed 7.3.2.11. Warning 0 (WARNING_0) 7.3.2.12. Fatal Error (FATAL_ERROR_0) 7.3.2.13. Monitor 0 (MON_) 7.3.2.14. Total Entries (TOTAL_ENTRIES) 7.3.2.15. Max. Rehouse Iterations (Max_Rehouse_Iterations) 7.3.2.16. Statistics Control (STATS_CTRL) 7.3.2.17. Active Table Entries (TABLE_ENTRIES) 7.3.2.18. Key_N 7.3.2.19. Result_N
7.4. TCAM Registers x
7.4.1. Device Feature Header (DFH)-Specific Registers 7.4.2. General TCAM Registers
7.4.1. Device Feature Header (DFH)-Specific Registers x
7.4.1.1. Field Names and Values
7.4.2. General TCAM Registers x
7.4.2.1. Version 7.4.2.2. Feature List 7.4.2.3. Interface Attribute Parameters 7.4.2.4. Scratch 7.4.2.5. Gen_Ctrl 7.4.2.6. Mgmt_Ctrl 7.4.2.7. Entry 7.4.2.8. Warning_0 7.4.2.9. Fatal_Error_0 7.4.2.10. Mon_0 7.4.2.11. Key_N 7.4.2.12. Result_N 7.4.2.13. Match_N 7.4.2.14. Mask_N
7.5. MBL Registers x
7.5.1. MBL DFH 7.5.2. General MBL Registers 7.5.3. Version 7.5.4. Mbl_scratch 7.5.5. Mbl_gen_ctrl 7.5.6. Mbl_mgmt_ctrl 7.5.7. Mbl_key_handle 7.5.8. Mbl_nxt_handle_req 7.5.9. Mbl_nxt_handle 7.5.10. Mbl_warning_0 7.5.11. Mbl_fatal_0 7.5.12. Mbl_mon_0 7.5.13. Mbl_total_entries 7.5.14. Mbl_total_rehashes 7.5.15. Mbl_max_used_bins 7.5.16. Mbl_stats_ctrl 7.5.17. Mbl_stats_result 7.5.18. Mbl_max_lkup_latency 7.5.19. Mbl_max_rehash_index 7.5.20. Mbl_key 7.5.21. Mbl_res
8. Parameterizing the Memory Subsystem IP x
8.1. Launching the Memory Subsystem IP 8.2. Parameterization Flow
8.2. Parameterization Flow x
8.2.1. Defining the Number of Memory Interfaces, Type, and Location 8.2.2. Selecting the Required Application Interfaces 8.2.3. Mapping Application to Memory Interfaces (Data Flow) 8.2.4. Generating IPs within the Memory Subsystem 8.2.5. Parameterizing Required EMIF, CAM, and MSA IPs
8.2.5. Parameterizing Required EMIF, CAM, and MSA IPs x
8.2.5.1. Parameterizing the External Memory Interface (EMIF) IP 8.2.5.2. Parameterizing the Memory-Specific Adapter 8.2.5.3. Parameterizing the Content-Addressable Memory (CAM) IP 8.2.5.4. Parameterizing the External Memory Interfaces Calibration IP 8.2.5.5. Saving the IPs Within the Memory Subsystem 8.2.5.6. Propagation of Changes Across IPs within the Memory Subsystem IP
9. Simulating a Design Example x
9.1. Generating a Design Example 9.2. Generated Directory Structure for the Design Example 9.3. Steps for Simulation 9.4. Generating Traffic with the Test Engine IP
1. About the Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP
2. Introduction to Memory Subsystem IP
3. Memory Subsystem IP Architecture and Feature Description
4. Memory Subsystem Features
5. Memory Subsystem Interfaces and Signals
6. Memory Subsystem User Operations
7. Memory Subsystem Register Descriptions
8. Parameterizing the Memory Subsystem IP
9. Simulating a Design Example
10. Document Revision History for Agilex™ 7 F-Series and I-Series FPGA Memory Subsystem IP User Guide

5.1. AXI Memory Mapped (AXI-MM) Interface

The AXI-MM interface offers the following features:
  • Supports AXI4.
  • Supports burst lengths of 1–256.
  • Supports the incremental (INCR) burst type only — no WRAP and FIXED support.
  • Does not support QOS, unaligned access, or narrow transfers.
  • Does not support region (AxREGION).
Table 16.  AXI MM Signals
Signal Name Direction Type Description
Write Address Channel
awaddr In Data Write address.
awid In Data Write address ID.
awlen In Data Burst length.
awsize In Data Burst size. This signal indicates the size of each transfer in the burst. Narrow transfer is not supported. The burst size must match the data bus width. For example:
  • For 128b data bus, burst size must be driven to 3'b100.
  • For 256b data bus, burst size must be driven to 3'b101.
  • For 512b data bus, burst size must be driven to 3'b110.
awburst In Data Burst type. The burst type and the size information, determine how the address for each transfer within the burst is calculated. The FPGA supports only INCR burst type.
awqos In Data QoS or priority. Multi-VC priority value of 0 is highest priority.
awuser In Data User signal (optional).
awvalid Out Control Write address valid.
awready Out Control Write address ready. Memory Sub-System keeps AXI-MM interface READY deasserted in REQ and DATA channel until it is ready (in place of formerly init_done).
Write Data Channel
wdata In Data Write data.
wstrb In Data Write strobe.
wlast In Data Write last, indicate last transfer in a write burst.
wuser In Data User signal (optional).
wvalid In Control Write data valid.
wready Out Control Write data ready. Memory Sub-System keeps AXI-MM interface READY deasserted in REQ and DATA channel until it is ready (in place of formerly init_done).
Write Response Channel
bid Out Data Write response ID.
bresp Out Data Write response.
bvalid Out Control Write response valid.
bready In Control Write response ready.
Read Address Channel
araddr In Data Read address.
arid In Data Read address ID.
arlen In Data Burst length.
arsize In Data Burst size. This signal indicates the size of each transfer in the burst. Narrow transfer is not supported. The burst size must match the data bus width. For example:
  • For 128b data bus, burst size must be driven to 3'b100.
  • For 256b data bus, burst size must be driven to 3'b101.
  • For 512b data bus, burst size must be driven to 3'b110.
arburst In Data Burst type. The burst type and the size information, determine how the address for each transfer within the burst is calculated. The FPGA supports only INCR burst type.
arqos In Data QoS or priority. See awqos for additional description about multi-VC.
aruser In Data User signal (optional).
arvalid In Control Read address valid.
arready Out Control Read address ready. Memory Sub-System keeps AXI-MM interface READY deasserted in REQ and DATA channel until it is ready (in place of formerly init_done).
Read Data Channel
rid Out Data Read data ID.
rresp Out Data Read data response.
rdata Out Data Read data.
rlast Out Data Read last, indicate last transfer in a read burst.
ruser Out Data User signal (optional).
rvalid Out Control Read data valid.
rready In Control Read data ready.
awprot In   Protection Type. AWPROT_WIDTH default value is 3. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
Value Protection Type
3’b000 No Protection
3’b001 SAI Enabled

When SAI Enabled is selected, use AWUSER_SAI field to check access privilege. Treat access as Device_Untrusted when No Protection is selected.

awuser.sai[SAI_WIDTH-1:0] In Control Write security attribute.
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