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5.1. Migrating Nios® II Processor to Nios® V Processor
5.2. Timer
5.3. Interrupt
5.4. Ethernet Stack
5.5. Bootloader
5.6. Data and Instruction Cache
5.7. Tightly Coupled Memory
5.8. Custom Instructions
5.9. Error Correction Code
5.10. Intel® HAL Settings
5.11. Micrium MicroC/OS-II BSP Settings
5.12. Software Packages
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5.2. Timer
Nios® V processor provides an internal timer functionality which allows you to configure your system clock timer and timestamp timer to use the internal timer. The Nios® V processor internal timer is a 64-bit counters that increment at the processor's clock frequency. The timer removes the need for an additional timer component. The Nios® II and Nios® V processors are compatible with the legacy method using the altera_avalon_timer peripheral and HAL driver.
If the Nios® II processor system use system clock timer, timestamp timer or both, there are two migration options:
- Reuse the existing external Interval Timer. You can disable the Nios® V processor Internal Timer as shown in the following figure (by disconnecting timer_sw_agent from data_manager).
Figure 42. Disabling Internal Timer
- Replace the existing external Interval Timer with Nios® V processor Internal Timer. You can enable the Nios® V processor Internal Timer as shown in the following figure (by connecting timer_sw_agent to data_manager), and remove the existing external Interval Timer.
Figure 43. Enabling Internal Timer
Figure 44. Timer BSP Settings
Related Information