AN 978: Nios® V Processor Migration Guidelines

ID 773196
Date 11/25/2024
Public
Document Table of Contents

6.1. Timer

Nios® V processor provides an internal timer functionality which allows you to configure your system clock timer and timestamp timer to use the internal timer. The Nios® V processor internal timer is a 64-bit counter that increments at the processor's clock frequency. The timer removes the need for an additional timer component. The Nios® II and Nios® V processors are compatible with the legacy method using the altera_avalon_timer peripheral and HAL driver.

If the Nios® II processor system uses system clock timer, timestamp timer or both, there are two migration options:
  • Reuse the existing external Interval Timer. You can disable the Nios® V processor Internal Timer as shown in the following figure (by disconnecting timer_sw_agent from data_manager).
    Figure 43. Disabling Internal Timer
  • Replace the existing external Interval Timer with Nios® V processor Internal Timer. You can enable the Nios® V processor Internal Timer as shown in the following figure (by connecting timer_sw_agent to data_manager), and remove the existing external Interval Timer.
    Figure 44. Enabling Internal Timer
After that, you must select the internal timer as the new timer in the BSP settings.
Figure 45. Timer BSP Settings