AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Ethernet Stack 6.4. Bootloader 6.5. Data and Instruction Cache 6.6. Tightly Coupled Memory 6.7. Custom Instructions 6.8. Error Correction Code 6.9. Intel® HAL Settings 6.10. Micrium MicroC/OS-II BSP Settings 6.11. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

5.1.1.2. IP Parameter Configuration

In the Nios® V/c processor, the following parameters are provided for you to configure:

  • CPU Architecture—Apply the Avalon® Memory Mapped instruction and data buses. When disabled, the buses are Arm* AMBA* AXI-4 Lite.
  • Use Reset Request—Exposes the reset request interface. You can enable this optional interface based on your needs requirement.
  • Reset Agent and Reset Offset—Configures the processor reset vector, equivalent to Reset Vector and Reset Offset in Nios® II/e processor.
  • ECC— Nios® V/c processor supports ECC Error Detection and Status Reporting on embedded memory blocks within the core.
The figures below display the configuration settings of the Nios V/c processor.
Figure 16.  Nios® V/c Processor – IP Parameter Editor
Table 11.  IP Parameter Editor Configuration
IP Parameter Editor Nios® V/c Processor Nios® II/e Processor
Reset Vector Navigate to Vectors. Navigate to,Vector > Reset Vector
Exception Vector Define as .exceptions in BSP Editor > Linker Section Mappings Navigate to, Vector > Exception Vector
JTAG Debug — Navigate to, JTAG Debug > JTAG Debug Settings
ECC

Navigate to ECC

Navigate to Advanced Features > General > ECC Present
CPU Reset Request Navigate to Use Reset Request Navigate to Advanced Features > General > Include cpu_resetrequest and cpu_resettaken signals
CPUID Value — Navigate to Advanced Features > General > CPUID control register value
Generate Trace File — Navigate to Advanced Features > General > Generate trace file during RTL simulation
RAM Memory Protection —

Navigate to Advanced Features RAM Memory Protection

The figures below display the configuration settings of the Nios® II/e processor.
Figure 17.  Nios® II/e Processor – IP Parameter Editor (Vector Tab)
Figure 18.  Nios® II/e Processor – IP Parameter Editor (JTAG Debug Tab)
Figure 19.  Nios® II/e Processor – IP Parameter Editor (Advanced Features Tab)
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