AN 978: Nios® V Processor Migration Guidelines

ID 773196
Date 11/25/2024
Public
Document Table of Contents

5.1.1.1. Signal and Interface Mapping

Table 9.  Primary Interface
Interface Nios® V Processor Nios® II Processor Description
Clock clock clock Similar clock input
Reset reset reset Similar hard reset
Debug reset debug_reset_request Mainly used to issue debug reset from CLI or IDE. By default, this feature is enabled in Nios® II/e processor. However, Nios® V/c is not supporting debug features.
Interrupts irq Nios® II/e processor supports 32 platform interrupts. Nios® V/c processor does not support interrupts.
Debug debug_mem_slave Allow JTAG download and debug. Nios® V/c processor does not support debug features.
Data bus data_manager data_master
  • Nios® II/e processor uses Avalon® memory-mapped interface.
  • Nios® V/c processor uses Arm* AMBA* AXI-4 Lite by default. You can switch to Avalon® memory-mapped interface.
Instruction bus instruction_manager instruction_master
  • Nios® II/e processor uses Avalon memory-mapped interface.
  • Nios® V/c processor uses Arm AMBA AXI-4 Lite by default. You can switch to Avalon® memory-mapped interface.
Custom instruction custom_instruction_master Nios® V/c does not support custom instruction.
Table 10.  Optional Interface
Interface Nios® V Processor Nios® II Processor Description
Debug request
  • debugreq
  • debugack
Nios® V/c processor does not support debug requests.
CPU reset request
  • cpu_resetreq_resetreq
  • cpu_resetreq_ack
  • cpu_resetrequest
  • cpu_resettaken
Same application
ECC event cpu_ecc_status ecc_event_bus Nios® V/c processor supports ECC on embedded memory blocks of the core. Nios® V processor supports error detection and status reporting, but not ECC recovery.