AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component Nios® V Processor BSP Regeneration Nios® V Processor APP Regeneration
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Ethernet Stack 6.4. Bootloader 6.5. Data and Instruction Cache 6.6. Tightly Coupled Memory 6.7. Custom Instructions 6.8. Error Correction Code 6.9. Intel® HAL Settings 6.10. Micrium MicroC/OS-II BSP Settings 6.11. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

4.2.1.2. Software Component

The software development flow starts with the creation of board support package (BSP) and application (APP). Altera recommends creating a software folder with app and bsp sub-folders inside your Quartus® Prime project directory. Nios® II processor software also has the same file organization.
Figure 3.  Nios® V Processor Software Project File Directory
Note: Generated Nios® II processor software files are not compatible with the Nios® V processor. You need to regenerate the Nios® V processor BSP and APP project.

Nios® V Processor BSP Regeneration

  1. Open the BSP Editor in Nios® V Command Shell with the command niosv-bsp-editor.
  2. Select the design SOPCINFO file in the SOPC Information File field, then click OK.
  3. The window assigns BSP target directory and BSP Settings File name to default locations.
    Figure 4. New BSP Window
  4. Apply the same Nios® II processor BSP settings into the Nios® V processor BSP settings. Refer to Intel HAL Settings to replicate the BSP Settings.
    Figure 5.  Nios® V Processor BSP Settings
  5. Select the appropriate memory region for exception vector in BSP Editor > Linker Script.
    Figure 6. Linker Script
  6. Click Generate BSP to create a new BSP project for Nios® V processor.

Nios® V Processor APP Regeneration

  1. Copy the Nios® II application source codes into the APP folder.
  2. Start the Nios V Command Shell.
  3. Run niosv-app command to create an APP CMakeLists.txt file.
    niosv-app -b=<BSP directory> -a=<APP directory> -s=<Nios II application source codes>
  4. Run CMake executable.
    cmake -B <APP directory>/build -S <APP directory> -G “Unix Makefiles”
  5. Run Make executable. After successful Make, the Nios® V processor software ELF file is located in the <APP directory>/build folder.
    make -C <APP directory>/build
  6. Download the software ELF file into the Nios® V processor system.
    niosv-download <Nios V ELF file>
  7. Open JTAG UART terminal to print the Hello World message.
    juart-terminal

Alternatively, you can use Ashling* RiscFree* IDE for Intel® FPGAs for Nios® V processor software development. After the BSP creation and APP creation, you can import both folders into the workspace of Ashling* RiscFree* IDE for Intel® FPGAs to continue.

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