AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Ethernet Stack 6.4. Bootloader 6.5. Data and Instruction Cache 6.6. Tightly Coupled Memory 6.7. Custom Instructions 6.8. Error Correction Code 6.9. Intel® HAL Settings 6.10. Micrium MicroC/OS-II BSP Settings 6.11. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

6.9. Intel® HAL Settings

The Nios® II processor embedded peripherals HAL driver is backward compatible with the Nios® V processor with the following _sw.tcl settings changes.
Table 34.  Changes in the _sw.tcl Settings for the Nios® V Processor
Nios® V Processor (hal.*) Nios® II Processor (hal.*)
enable_instruction_related_exceptions_api enable_instruction_related_exceptions_api
max_file_descriptors max_file_descriptors
— disable_startup_thread_sync
— enable_small_stack
— exclude_default_exception
sys_clk_timer sys_clk_timer
timestamp_timer timestamp_timer
linker.allow_code_at_reset linker.allow_code_at_reset
linker.enable_alt_load linker.enable_alt_load
linker.enable_alt_load_copy_exceptions linker.enable_alt_load_copy_exceptions
linker.enable_alt_load_copy_rodata linker.enable_alt_load_copy_rodata
linker.enable_alt_load_copy_rwdata linker.enable_alt_load_copy_rwdata
linker.enable_exception_stack linker.enable_exception_stack
linker.exception_stack_memory_region_name linker.exception_stack_memory_region_name
linker.exception_stack_size linker.exception_stack_size
— linker.enable_interrupt_stack
— linker.interrupt_stack_memory_region_name
— linker.interrupt_stack_size
linker.use_picolibc —
toolchain.prefix —
toolchain.enable_executable_overrides —
toolchain.ar make.ar
toolchain.as make.as
toolchain.cc make.cc
toolchain.cxx make.cxx
toolchain.objdump —
—

make:

  • build_pre_process
  • build_post_process
  • ar_pre_process
  • ar_post_process
  • as_pre_process
  • as_post_process
  • cc_pre_process
  • cc_post_process
  • cxx_pre_process
  • cxx_post_process
— make.bsp_arflags
make.asflags make.bsp_asflags
make.cflags_debug make.bsp_cflags_debug
make.cflags_defined_symbols make.bsp_cflags_defined_symbols
make.cflags_optimization make.bsp_cflags_optimization
make.cflags_undefined_symbols make.bsp_cflags_undefined_symbols
make.cflags_user_flags make.bsp_cflags_user_flags
make.cflags_warnings make.bsp_cflags_warnings
make.cxx_flags make.bsp_cxx_flags
— make.bsp_inc_dirs
make.link_flags —
make.objdump_flags —
make.enable_cflag_fstack_protector_strong make.enable_cflag_fstack_protector_strong
make.enable_cflag_wformat_security make.enable_cflag_wformat_security
—

make.ignore_system_derived:

  • big_endian
  • fpu_present
  • hardware_divide_present
  • hardware_fp_cust_inst_divider_present
  • hardware_fp_cust_inst_no_divider_present
  • sopc_simulation_enabled
  • debug_core_present
  • hardware_multiplier_present
  • hardware_mulx_present
  • sopc_system_base_address
  • sopc_system_id
  • sopc_system_timestamp
— make.rm
— custom_newlib_flags
enable_c_puls_plus enable_c_plus_plus
enable_clean_exit enable_clean_exit
enable_exit enable_exit
— enable_gprof
enable_reduced_device_drivers enable_reduced_device_drivers
enable_lightweight_device_driver_api enable_lightweight_device_driver_api
— enable_mul_div_emulation
enable_runtime_stack_checking enable_runtime_stack_checking
enable_sim_optimize enable_sim_optimize
— enable_small_c_library
— enable_sopc_sysid_check
log_port log_port
log_flags log_flags
stderr stderr
stdin stdin
stdout stdout
— thread_stack_size
Level Two Title