AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Ethernet Stack 6.4. Bootloader 6.5. Data and Instruction Cache 6.6. Tightly Coupled Memory 6.7. Custom Instructions 6.8. Error Correction Code 6.9. Intel® HAL Settings 6.10. Micrium MicroC/OS-II BSP Settings 6.11. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

6.6. Tightly Coupled Memory

Nios® II/f and Nios® V/g processors support tightly coupled memory (TCM).
Table 30.  TCM Characteristics
TCM Nios® V/g Processor Nios® II/f Processor
Number of Instruction TCM (ITCM) Two Four
Number of Data TCM (DTCM) Two Four
Memory Type Dual-port (Internal port to processor and external subordinate port).

Depends on the connected on-chip memory:

  • Single-port
  • Dual-port
TCMs Size 0 Bytes (Disabled), up to 512 MBytes Depends on the connected on-chip memory.
TCMs Location Internal within Nios® V processor core (internal RAM). External to Nios® II processor core (system RAM).
TCMs Instantiation Instantiated within the processor upon enable.
  • Expose TCM memory interface master port upon enable.
  • A connection must be made to any on-chip memory.
Memory Initialization Supports HEX or MIF file. Supports HEX or MIF file.
Table 31.  TCM Use Cases
TCM Nios® V/g Processor Nios® II/f Processor
Memory Region
  • Dual-port ITCM:
    • Instruction memory region (Internal connection to processor instruction bus)
    • Data memory region (Connects ITCM subordinate port to Nios V processor data_manager port)
  • Single-port DTCM: Data memory region (Internal connection to processor data bus).

  • Single-port ITCM: Instruction memory region (Connects to ITCM master port)
  • Dual-port ITCM:
    • Instruction memory region (Connects 1st slave port to ITCM master port)
    • Data memory region (Connects 2nd slave port to Nios II processor data_master port)
  • Single-port DTCM: Data memory region (Connects to DTCM master port)
Nios® V Processor Application Execute-In-Place from ITCM Initialize dual-port ITCM and single-port DTCM (or system RAM) with Application HEX file.
  • Initialize single-port ITCM and DTCM (or system RAM) with Application HEX file.
  • Initialize dual-port ITCM with Application HEX file.
alt_load() with ITCM Supported with dual-port ITCM and single-port DTCM.
  • Not supported with single-port ITCM.
  • Supported with dual-port ITCM.
Download Nios® V Processor Application into ITCM Supported with dual-port ITCM and single-port DTCM.
  • Not supported with single-port ITCM.
  • Supported with dual-port ITCM.
External Host Interface
  • Accessible by external host or processor core (for dual-port TCMs).
  • The interface is AXI4-Lite Subordinate Port.
  • Accessible by external host or processor core (for dual-port TCMs).
  • The interface is Avalon® Memory-Mapped Slave Port.
Figure 46. Tightly-Coupled Memory in Nios® V/g Processor
Figure 47. Tightly-Coupled Memory with Nios® II/f Processor
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