AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Ethernet Stack 6.4. Bootloader 6.5. Data and Instruction Cache 6.6. Tightly Coupled Memory 6.7. Custom Instructions 6.8. Error Correction Code 6.9. Intel® HAL Settings 6.10. Micrium MicroC/OS-II BSP Settings 6.11. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

6.5. Data and Instruction Cache

Nios® II/f and Nios® V/g processors support cache.

Table 29.  Cache Comparison Between Nios® V and Nios® II Processors
Cache Nios® V/g Processor Nios® II/f Processor
Instruction Cache
  • 1KB 3
  • 2KB
  • 4KB
  • 8KB
  • 16KB
  • 04
  • 512B
  • 1KB
  • 2KB
  • 4KB
  • 8KB
  • 16KB
  • 32KB
  • 64KB
Data Cache
  • 1KB
  • 2KB
  • 4KB
  • 8KB
  • 16KB
  • 0
  • 512B
  • 1KB
  • 2KB
  • 4KB
  • 8KB
  • 16KB
  • 32KB
  • 64KB
Cache Bypass Method Peripheral Regions
  • Bit-31 cache bypass
  • Cache bypass instructions
  • Peripheral Regions
The processors use the peripheral regions to define non-cacheable address space for peripherals such as UART, PIO, DMA, and others. Both Nios® II/f and Nios® V/g processors support peripheral regions. Nios® V/g processor supports two separate peripheral regions, and Nios® II/f processor supports only one.
  • For Nios® II/f processor (with caches enabled), it is optional to use a peripheral region when using peripherals.
  • For Nios® V/g processor, you must place your peripherals in a peripheral region. Failure to do so can cause the processor system to malfunction.

If you do not define the peripherals regions, Platform Designer prompts the following warning message:

No peripheral regions have been defined. If your design contains any peripherals such as UART, PIO, DMA, etc, they must be placed within a peripheral region.

3 Nios® V/g processor requires a minimum allocation of 1KB cache size.
4 You can disable the cache in the Nios® II/f processor.
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