AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Migration Mapping 4. Design Flow Comparison 5. Migration by Use Case 6. Document Revision History for AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Difference in the Design Flow 4.2. Design Migration from Nios® II Processor to Nios® V Processor
4.2. Design Migration from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Migration by Use Case x
5.1. Migrating Nios® II Processor to Nios® V Processor 5.2. Timer 5.3. Interrupt 5.4. Ethernet Stack 5.5. Bootloader 5.6. Data and Instruction Cache 5.7. Tightly Coupled Memory 5.8. Custom Instructions 5.9. Error Correction Code 5.10. Intel® HAL Settings 5.11. Micrium MicroC/OS-II BSP Settings 5.12. Software Packages
5.1. Migrating Nios® II Processor to Nios® V Processor x
5.1.1. Processor IP Instantiation in Platform Designer 5.1.2. Migrating Nios® II/e Processor to Nios® V/c Processor 5.1.3. Migrating Nios® II Processor to Nios® V/m Processor 5.1.4. Migrating Nios® II/f Processor to Nios® V/g Processor
5.1.2. Migrating Nios® II/e Processor to Nios® V/c Processor x
5.1.2.1. Nios® V Processor Hardware Migration 5.1.2.2. Nios® V Processor Software Migration
5.1.2.1. Nios® V Processor Hardware Migration x
5.1.2.1.1. Signal and Interface Mapping 5.1.2.1.2. IP Parameter Configuration 5.1.2.1.3. BSP Project Generation
5.1.2.2. Nios® V Processor Software Migration x
5.1.2.2.1. Command-Line Build Flow 5.1.2.2.2. IDE Build Flow
5.1.3. Migrating Nios® II Processor to Nios® V/m Processor x
5.1.3.1. Nios® V Processor Hardware Migration 5.1.3.2. Nios® V Processor Software Migration
5.1.3.1. Nios® V Processor Hardware Migration x
5.1.3.1.1. Signal and Interface Mapping 5.1.3.1.2. IP Parameter Configuration 5.1.3.1.3. BSP Project Generation
5.1.3.2. Nios® V Processor Software Migration x
5.1.3.2.1. Command-Line Build Flow 5.1.3.2.2. IDE Build Flow
5.1.4. Migrating Nios® II/f Processor to Nios® V/g Processor x
5.1.4.1. Nios® V Processor Hardware Migration 5.1.4.2. Nios® V Processor Software Migration
5.1.4.1. Nios® V Processor Hardware Migration x
5.1.4.1.1. Signal and Interface Mapping 5.1.4.1.2. IP Parameter Configuration 5.1.4.1.3. BSP Project Generation
5.1.4.2. Nios® V Processor Software Migration x
5.1.4.2.1. Command-Line Build Flow 5.1.4.2.2. IDE Build Flow
1. Overview
2. Architecture Comparison
3. Processor Core Migration Mapping
4. Design Flow Comparison
5. Migration by Use Case
6. Document Revision History for AN 978: Nios® V Processor Migration Guidelines

5.1.4.1.1. Signal and Interface Mapping

Table 20.  Primary Interface
Interface Nios® V Processor Nios® II Processor Description
Clock clock clock Similar clock input
Reset reset reset Similar hard reset
Debug reset
  • dbg_reset_out
  • ndm_reset_in
debug_reset_request Mainly used to issue debug reset from CLI or IDE. By default, this feature is enabled in Nios® II/f processor but disabled in Nios® V/g processor.
Interrupts platform_irq_rx irq Nios® II/f processor supports32 platform interrupts. Nios® V/g processor supports 16 platform interrupts.
Timer and Software Interrupt Module timer_sw_agent — Only supported in Nios® V processor. By default, it is connected to the data manager.
Debug dm_agent debug_mem_slave Allow JTAG download and debug. For Nios® V/g processor, by default, it is connected to the data manager and instruction manager.
Data bus data_manager data_master
  • Nios® II/f uses Avalon® memory-mapped interface
  • Nios® V/g processor uses Arm* AMBA* AXI-4
Instruction bus instruction_manager instruction_manager
  • Nios® II/f uses Avalon® memory-mapped interface
  • Nios® V/g processor uses Arm* AMBA* AXI-4
Custom instruction —

(Instantiate in the Nios V Processor IP Parameter Editor)

custom_instruction_master
  • Nios® II/f implements custom instruction as primary interface.
  • Nios® V/g implements custom instruction as optional interface.
Table 21.  Optional Interface
Interface Nios® V Processor Nios® II Processor Description
Debug request —
  • debugreq
  • debugack
Nios® V/g processor does not support debug requests.
CPU reset request
  • cpu_resetreq_resetreq
  • cpu_resetreq_ack
  • cpu_resetrequest
  • cpu_resettaken
Same application
ECC event cpu_ecc_status ecc_event_bus
  • Nios® V/g processor supports ECC on embedded memory blocks of the core.
  • Nios® V processor supports error detection and status reporting, but not ECC recovery.
Custom instruction ci_custom<opcode>_<funct7[6:4]> —
  • Nios® II/f implements custom instruction as primary interface.
  • Nios® V/g implements custom instruction as optional interface.
Tightly coupled memory (TCM
  • instruction_tcs
  • data_tcs
tightly_coupled_master Refer to the section Tightly Coupled Memory for more information.
Related Information
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