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5.2.1.2. IP Parameter Configuration
The following are the parameters that you need to configure in the Nios® V/m processor:
- Debug and Use Reset Request—the Nios V Processor IP Parameter Editor exposes the debug and reset request interface. Depending on your requirement, you can enable these optional interfaces.
- Reset Agent and Reset Offset—configures the processor reset vector. Equivalent to the Reset Vector and Reset Offset in the Nios® II processors.
- CPU Architecture—instantiates the non-pipelined Nios® V/m processor. It has smaller logic area, but lower IPC performance than pipelined. Optionally, you can apply the following configurations:
- Apply the Avalon® Memory Mapped instruction and data buses. When disabled, these buses use the Arm* AMBA* AXI-4 Lite protocol.
- Assign a value to the Hart ID register (mhartid).
- ECC—supports ECC error detection and status reporting on embedded memory blocks within the core.
The figure below display the configuration settings of the Nios® V/m processor.
Figure 22. Nios® V/m Microcontroller Intel® FPGA IP – IP Parameter Editor
| IP Parameter Editor | Nios® V Processor | Nios® II Processor |
|---|---|---|
| Reset Vector | Navigate to Vectors | Navigate to Vector > Reset Vector |
| Exception Vector | Define as .exceptions in BSP Editor > Linker Section Mappings. | Navigate to Vector > Exception Vector |
| Fast TLB Miss Exception Vector | — | Navigate to Vector > Fast TLB Miss Exception Vector |
| Cache and Memory Interfaces | — | Navigate to Caches and Memory Interfaces |
| Arithmetic Instructions | — | Navigate to Arithmetic Instructions |
| MMU and MPU Settings | — | Navigate to MMU and MPU Settings |
| JTAG Debug | Navigate to Debug > Enable Debug | Navigate to JTAG Debug > JTAG Debug Settings |
| Enable Reset from Debug Module | Navigate to Debug > Enable Reset from Debug Module | Enable when JTAG Debug is enabled |
| ECC | Navigate to ECC | Navigate to Advanced Features > General > ECC Present |
| Interrupt Controller | Internal controller only | Navigate to Advanced Features > Interrupt controller |
| Shadow Register | — | Navigate to Advanced Features > Number of shadow register sets |
| CPU Reset Request | Navigate to Use Reset Request | Navigate to Advanced Features > General > Include cpu_resetrequest and cpu_resettaken signals |
| CPUID Value | Navigate to CPU Architecture > mhartid CSR value | Navigate to Advanced Features > General > CPUID control register value |
| Generate Trace File | — | Navigate to Advanced Features > General > Generate trace file during RTL simulation |
| Exception Checking | Enabled by default | Navigate to Advanced Features > Exception Checking |
| Branch Prediction | — | Navigate to Advanced Features > Branch Prediction |
| RAM Memory Protection | — | Navigate to Advanced Features > RAM Memory Protection |
| Non-pipelined Configuration | Navigate to CPU Architecture > Enable Pipelining in CPU | — |
The following figures display the configuration settings of both Nios® II/e and Nios® II/f processor.
Figure 23. Nios® II Processor – IP Parameter Editor (Vector Tab)
Figure 24. Nios® II Processor – IP Parameter Editor (Caches and Memory Interfaces Tab)
Figure 25. Nios® II Processor – IP Parameter Editor (Arithmetic Instructions Tab)
Figure 26. Nios® II Processor – IP Parameter Editor (MMU and MPU Settings Tab)
Figure 27. Nios® II Processor – IP Parameter Editor (JTAG Debug Tab)
Figure 28. Nios® II Processor – IP Parameter Editor (Advanced Features Tab)
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