AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Migration Mapping 4. Design Flow Comparison 5. Migration by Use Case 6. Document Revision History for AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Difference in the Design Flow 4.2. Design Migration from Nios® II Processor to Nios® V Processor
4.2. Design Migration from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Migration by Use Case x
5.1. Migrating Nios® II Processor to Nios® V Processor 5.2. Timer 5.3. Interrupt 5.4. Ethernet Stack 5.5. Bootloader 5.6. Data and Instruction Cache 5.7. Tightly Coupled Memory 5.8. Custom Instructions 5.9. Error Correction Code 5.10. Intel® HAL Settings 5.11. Micrium MicroC/OS-II BSP Settings 5.12. Software Packages
5.1. Migrating Nios® II Processor to Nios® V Processor x
5.1.1. Processor IP Instantiation in Platform Designer 5.1.2. Migrating Nios® II/e Processor to Nios® V/c Processor 5.1.3. Migrating Nios® II Processor to Nios® V/m Processor 5.1.4. Migrating Nios® II/f Processor to Nios® V/g Processor
5.1.2. Migrating Nios® II/e Processor to Nios® V/c Processor x
5.1.2.1. Nios® V Processor Hardware Migration 5.1.2.2. Nios® V Processor Software Migration
5.1.2.1. Nios® V Processor Hardware Migration x
5.1.2.1.1. Signal and Interface Mapping 5.1.2.1.2. IP Parameter Configuration 5.1.2.1.3. BSP Project Generation
5.1.2.2. Nios® V Processor Software Migration x
5.1.2.2.1. Command-Line Build Flow 5.1.2.2.2. IDE Build Flow
5.1.3. Migrating Nios® II Processor to Nios® V/m Processor x
5.1.3.1. Nios® V Processor Hardware Migration 5.1.3.2. Nios® V Processor Software Migration
5.1.3.1. Nios® V Processor Hardware Migration x
5.1.3.1.1. Signal and Interface Mapping 5.1.3.1.2. IP Parameter Configuration 5.1.3.1.3. BSP Project Generation
5.1.3.2. Nios® V Processor Software Migration x
5.1.3.2.1. Command-Line Build Flow 5.1.3.2.2. IDE Build Flow
5.1.4. Migrating Nios® II/f Processor to Nios® V/g Processor x
5.1.4.1. Nios® V Processor Hardware Migration 5.1.4.2. Nios® V Processor Software Migration
5.1.4.1. Nios® V Processor Hardware Migration x
5.1.4.1.1. Signal and Interface Mapping 5.1.4.1.2. IP Parameter Configuration 5.1.4.1.3. BSP Project Generation
5.1.4.2. Nios® V Processor Software Migration x
5.1.4.2.1. Command-Line Build Flow 5.1.4.2.2. IDE Build Flow
1. Overview
2. Architecture Comparison
3. Processor Core Migration Mapping
4. Design Flow Comparison
5. Migration by Use Case
6. Document Revision History for AN 978: Nios® V Processor Migration Guidelines

5.1.3.1.2. IP Parameter Configuration

The following are the parameters that you need to configure in the Nios® V/m processor:

  • Debug and Use Reset Request—the Nios V Processor IP Parameter Editor exposes the debug and reset request interface. Depending on your requirement, you can enable these optional interfaces.
  • Reset Agent and Reset Offset—configures the processor reset vector. Equivalent to the Reset Vector and Reset Offset in the Nios® II processors.
  • CPU Architecture—instantiates the non-pipelined Nios® V/m processor. Smaller logic area, but lower IPC performance than pipelined Nios® V/m processor. Optionally, assign the Hart ID register (mhartid) value.
  • ECC—supports ECC error detection and status reporting on embedded memory blocks within the core.
The figures below display the configuration settings of the Nios® V/m processor.
Figure 22.  Nios® V/m Microcontroller Intel® FPGA IP – IP Parameter Editor
Table 16.  IP Parameter Editor Comparison
IP Parameter Editor Nios® V Processor Nios® II Processor
Reset Vector Navigate to Vectors Navigate to Vector > Reset Vector
Exception Vector Define as .exceptions in BSP Editor > Linker Section Mappings. Navigate to Vector > Exception Vector
Fast TLB Miss Exception Vector — Navigate to Vector > Fast TLB Miss Exception Vector
Cache and Memory Interfaces — Navigate to Caches and Memory Interfaces
Arithmetic Instructions — Navigate to Arithmetic Instructions
MMU and MPU Settings —

Navigate to MMU and MPU Settings

JTAG Debug Navigate to Debug > Enable Debug Navigate to JTAG Debug > JTAG Debug Settings
Enable Reset from Debug Module Navigate to Debug > Enable Reset from Debug Module Enable when JTAG Debug is enabled
ECC Navigate to ECC Navigate to Advanced Features > General > ECC Present
Interrupt Controller Internal controller only Navigate to Advanced Features > Interrupt controller
Shadow Register — Navigate to Advanced Features > Number of shadow register sets
CPU Reset Request Navigate to Use Reset Request Navigate to Advanced Features > General > Include cpu_resetrequest and cpu_resettaken signals
CPUID Value Navigate to CPU Architecture > mhartid CSR value Navigate to Advanced Features > General > CPUID control register value
Generate Trace File — Navigate to Advanced Features > General > Generate trace file during RTL simulation
Exception Checking Enabled by default Navigate to Advanced Features > Exception Checking
Branch Prediction — Navigate to Advanced Features > Branch Prediction
RAM Memory Protection — Navigate to Advanced Features > RAM Memory Protection
Non-pipelined Configuration Navigate to CPU Architecture > Enable Pipelining in CPU —

The following figures display the configuration settings of both Nios® II/e and Nios® II/f processor.

Figure 23.  Nios® II Processor – IP Parameter Editor (Vector Tab)
Figure 24.  Nios® II Processor – IP Parameter Editor (Caches and Memory Interfaces Tab)
Figure 25.  Nios® II Processor – IP Parameter Editor (Arithmetic Instructions Tab)
Figure 26.  Nios® II Processor – IP Parameter Editor (MMU and MPU Settings Tab)
Figure 27.  Nios® II Processor – IP Parameter Editor (JTAG Debug Tab)
Figure 28.  Nios® II Processor – IP Parameter Editor (Advanced Features Tab)
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