AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Migration Mapping 4. Design Flow Comparison 5. Migration by Use Case 6. Document Revision History for AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Difference in the Design Flow 4.2. Design Migration from Nios® II Processor to Nios® V Processor
4.2. Design Migration from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Migration by Use Case x
5.1. Migrating Nios® II Processor to Nios® V Processor 5.2. Timer 5.3. Interrupt 5.4. Ethernet Stack 5.5. Bootloader 5.6. Data and Instruction Cache 5.7. Tightly Coupled Memory 5.8. Custom Instructions 5.9. Error Correction Code 5.10. Intel® HAL Settings 5.11. Micrium MicroC/OS-II BSP Settings 5.12. Software Packages
5.1. Migrating Nios® II Processor to Nios® V Processor x
5.1.1. Processor IP Instantiation in Platform Designer 5.1.2. Migrating Nios® II/e Processor to Nios® V/c Processor 5.1.3. Migrating Nios® II Processor to Nios® V/m Processor 5.1.4. Migrating Nios® II/f Processor to Nios® V/g Processor
5.1.2. Migrating Nios® II/e Processor to Nios® V/c Processor x
5.1.2.1. Nios® V Processor Hardware Migration 5.1.2.2. Nios® V Processor Software Migration
5.1.2.1. Nios® V Processor Hardware Migration x
5.1.2.1.1. Signal and Interface Mapping 5.1.2.1.2. IP Parameter Configuration 5.1.2.1.3. BSP Project Generation
5.1.2.2. Nios® V Processor Software Migration x
5.1.2.2.1. Command-Line Build Flow 5.1.2.2.2. IDE Build Flow
5.1.3. Migrating Nios® II Processor to Nios® V/m Processor x
5.1.3.1. Nios® V Processor Hardware Migration 5.1.3.2. Nios® V Processor Software Migration
5.1.3.1. Nios® V Processor Hardware Migration x
5.1.3.1.1. Signal and Interface Mapping 5.1.3.1.2. IP Parameter Configuration 5.1.3.1.3. BSP Project Generation
5.1.3.2. Nios® V Processor Software Migration x
5.1.3.2.1. Command-Line Build Flow 5.1.3.2.2. IDE Build Flow
5.1.4. Migrating Nios® II/f Processor to Nios® V/g Processor x
5.1.4.1. Nios® V Processor Hardware Migration 5.1.4.2. Nios® V Processor Software Migration
5.1.4.1. Nios® V Processor Hardware Migration x
5.1.4.1.1. Signal and Interface Mapping 5.1.4.1.2. IP Parameter Configuration 5.1.4.1.3. BSP Project Generation
5.1.4.2. Nios® V Processor Software Migration x
5.1.4.2.1. Command-Line Build Flow 5.1.4.2.2. IDE Build Flow
1. Overview
2. Architecture Comparison
3. Processor Core Migration Mapping
4. Design Flow Comparison
5. Migration by Use Case
6. Document Revision History for AN 978: Nios® V Processor Migration Guidelines

2.1. Features Comparison

Table 1.  Core Architecture Comparison to Nios® II/e Processor
Feature Core Architecture Comparison
Nios® V/c Processor Non-pipelined Nios® V/m Processor Nios® II/e Processor
32-bit General Purpose Register (GPR) Yes Yes Yes
Pipelined Architecture​ — — —
Debug Module — Yes Yes
M Extn (Mul/Div)​ — ​ — ​ —
Custom Instructions​ — ​ — Yes
Cache Support​ — ​​ — ​​ —
Tightly Coupled Memory (TCM) — ​​ — ​​ —
Branch Prediction​ — — —
On-Chip Trace​ — — —

Error Correction Code (ECC)

 Yes Yes —

32-bit Floating Point Unit (FPU)

— — —

Memory Protection Unit (MPU)

 — — —

Memory Management Unit (MMU)

 — — —
Internal Timer — ​ Yes —
Machine Mode​ Yes Yes Yes​
User Mode​ — — —
Supervisor Mode​ — — —
Interrupt Controller — Yes Yes
Exception Handling — Yes Yes
Intel HAL​ Yes Yes Yes
uC-OS/II​ — Yes Yes
Zephyr​ — Yes —
FreeRTOS​ — Yes —
Embedded Linux​ — — —
Table 2.  Core Architecture Comparison to Nios II/f Processor
Feature Core Architecture Comparison
Nios® V/m Processor Nios® V/g Processor Nios® II/f Processor
32-bit General Purpose Register (GPR) Yes Yes Yes
Pipelined Architecture​ Yes Yes Yes
Debug Module Yes Yes Yes
M Extn (Mul/Div)​ ​ — Yes Yes
Custom Instructions​ ​ — Yes Yes
Cache Support​ ​​ — Yes Yes
Tightly Coupled Memory (TCM) ​​ — Yes Yes
Branch Prediction​ — — Yes
On-Chip Trace​ — — Yes
Error Correction Code (ECC) Yes Yes Yes
32-bit Floating Point Unit (FPU) — Yes (F Extn) Yes (FPH1 or FPH2)
Memory Protection Unit (MPU) — — Yes
Memory Management Unit (MMU) — — Yes
Internal Timer ​ Yes ​ Yes —
Machine Mode​ Yes Yes​ Yes
User Mode​ — — —
Supervisor Mode​ — — Yes​
Interrupt Controller Yes Yes Yes
Exception Handling Yes Yes Yes
Intel HAL​ Yes Yes Yes
uC-OS/II​ Yes Yes Yes
Zephyr​ Yes Yes —
FreeRTOS​ Yes Yes —
Embedded Linux​ — — Yes
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