AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 1/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Ethernet Stack 6.4. Bootloader 6.5. Data and Instruction Cache 6.6. Tightly Coupled Memory 6.7. Custom Instructions 6.8. Error Correction Code 6.9. Intel® HAL Settings 6.10. Micrium MicroC/OS-II BSP Settings 6.11. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

4.1. Differences in the Design Flow

Table 6.  Notable Consideration by Design Flow
Design Stage Nios® V Processor Nios® II Processor Notes
Quartus® Prime Project Creation Create a new project using the New Project Wizard. Create a new project using the New Project Wizard. None
Define and Generate System in the Platform Designer
  1. Instantiate the Nios® V processor core.
  2. Create a Nios® V processor system with basic peripherals.
  1. Instantiate the Nios® II processor core.
  2. Create a Nios® II processor system with basic peripherals.
  1. Nios® V processor has a similar interface as the Nios® II processor. You can replace the interface in Platform Designer.
  2. Refer to Table Processor Core Upgrade Paths for the processor core mapping guidelines.
  3. Refer to Table Primary Interface for the signals connection mapping guidelines.
Invoke the BSP Editor
  • For Quartus® Prime Pro Edition software:
    • Use Platform Designer.
  • For Quartus® Prime Standard Edition software:
    • Use Nios® V Command Shell with the command niosv-bsp-editor.
  • You can use the Nios® II Embedded Design Suite (Eclipse IDE) in both Quartus® Prime software editions.
  • Alternatively, you can use the following software:
    • For Quartus® Prime Pro Edition software, use Platform Designer.
    • For Quartus® Prime Standard Edition software, use Nios® II Command shell with the command nios2-bsp-editor.
Invoke the BSP Editor with a different tool.
Create system file for BSP Editor
  • For Quartus® Prime Pro Edition software, use .qsys file.
  • For Quartus® Prime Standard Edition software, use sopcinfo file.
For both Quartus® Prime software editions, use sopcinfo file. Different input file to create the BSP settings file.
Configure and generate the BSP
  1. Decide what features the BSP requires by specifying the components in the BSP and relevant settings.
  2. Generate the settings.bsp file using the following tools:
    • Option 1: BSP Editor in Platform Designer.
    • Option 2: niosv-bsp utility.
  3. Import the BSP folder into Ashling* RiscFree* IDE for Intel® FPGAs.
  1. Decide what features the BSP requires by specifying the components in the BSP and relevant settings.
  2. Generate the settings.bsp file using the following tools:
    • Option 1: BSP Editor in Nios® II EDS
    • Option 2: nios2-bsp utility.
  • Ashling* RiscFree* IDE for Intel® FPGAs does not support new Nios® V processor BSP project creation. You need to import the BSP project.
  • Apply different CLI command for BSP generation.
Generate the APP folder
  1. Develop the application code based on the hardware design.
  2. Generate an application build CMakeLists.txt using the niosv-app utility.
  3. Import the APP folder into Ashling* RiscFree* IDE for Intel® FPGAs.
  1. Develop the application code based on the hardware design.
  2. Generate an application build MakeFiles using the following tools:
    • Option 1: Nios® II EDS
    • Option 2: nios2-app-generate-makefile utility.
  • Ashling* RiscFree* IDE for Intel® FPGAs does not support new Nios® V processor APP project creation. You need to import the APP project.
  • Apply different CLI command for APP generation.
Build the ELF Use one of the following tools:
  • Option 1: Ashling* RiscFree* IDE for Intel® FPGAs.
  • Option 2: cmake and make command.
Use one of the following tools:
  • Option 1: Nios® II EDS
  • Option 2: make command
Different development tools build flow.
Download the ELF Use one of the following tools:
  • Option 1: Ashling* RiscFree* IDE for Intel® FPGAs.
  • Option 2: niosv-download command.
Use one of the following tools:
  • Option 1: Nios® II EDS
  • Option 2: nios2-download command.

Different development tools and ELF download command.
Open the JTAG UART Terminal

Use the juart-terminal command.

Use one of the following tools:
  • Option 1: Nios® II Console in Nios® II EDS

  • Option 2: nios2-terminal command.

  1. Ashling* RiscFree* IDE for Intel® FPGAs does not support native JTAG UART terminal. You can open the terminal using External Tools Configuration feature.
  2. Different open terminal command for JTAG UART Intel FPGA IP..
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