AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 1/27/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Ethernet Stack 6.4. Bootloader 6.5. Data and Instruction Cache 6.6. Tightly Coupled Memory 6.7. Custom Instructions 6.8. Error Correction Code 6.9. Intel® HAL Settings 6.10. Micrium MicroC/OS-II BSP Settings 6.11. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

7.2. Data Handling and Memory Operations

Table 40.  Assembly Language Comparison (Data Handling and Memory Operations)
Nios® II Processor Nios® V Processor
Operation Assembler Syntax Operation Assembler Syntax
Flushes the data cache line associated with address rA + σ(IMM16) based on line field. flushd IMM16(rA) Flush the data cache line associated with address xA + σ(IMM12) based on index field.

addi xA, xA, IMM12

lui xB, 0x000003e0

and xA, xA, xB

srli xA, xA, 5

cbo.flush.ix xA

Refer to the detailed steps for the Nios® V processor pseudo-instruction below:
  1. Compute effective address by the sum of xA with offset IMM12.
  2. Load based on cache size. In a 1 kilobytes cache, index bit field is 5-bit wide (0x3e0).
  3. Extract the value of the 5-bit index from address xA + σ(IMM12) using AND operation.
  4. Shift-right by 5 bits to remove offset bit field.
  5. Flush the data cache line associated with the index of address xA + σ(IMM12).
Flushes the data cache line currently caching address rA + σ(IMM16). flushda IMM16(rA) Flush the data cache line associated with address xA + σ(IMM12).

addi xA, xA, IMM12

cbo.flush 0(xA)

Flushes the instruction cache line associated with address rA. flushi rA To synchronize the instruction and data streams. fence.i
Flushes the processor pipeline of any prefetched instructions. flushp To synchronize the instruction and data streams. fence.i
Initializes the data cache line associated with address rA + σ(IMM16) based on line field. initd IMM16(rA) Initializes the data cache line associated with address xA + σ(IMM12) based on index field.

addi xA, xA, IMM12

lui xB, 0x00003fe0

and xA, xA, xB

srli xA, xA, 5

cbo.inval.ix xA

Refer to the detailed steps for the Nios® V processor pseudo-instruction below:
  1. Compute effective address by the sum of xA with offset IMM12.
  2. Load based on cache size. In a 16 kilobytes cache, index bit field is 9-bit wide (0x3fe0).
  3. Extract the value of the 9-bit index from address xA + σ(IMM12) using AND operation
  4. Shift-right by 5 bits to remove offset bit field.
  5. Initializes the data cache line associated with the index of address xA + σ(IMM12).
Initializes the data cache line currently caching address rA + σ(IMM16). initda IMM16(rA) Initializes the data cache line associated with address xA + σ(IMM12).

addi xA, xA, IMM12

cbo.inval 0(xA)

Initializes the instruction cache line associated with address rA. initi rA To synchronize the instruction and data streams. fence.i
Load Byte from Memory ldb rB, IMM16(rA) Load Byte from Memory lb xB, IMM12(xA)
Load Byte from I/O Peripheral. ldbio rB, IMM16(rA) Not Available in Nios® V processor -
Load Unsigned Byte from Memory ldbu rB, IMM16(rA) Load Unsigned Byte from Memory lbu xB, IMM12(xA)
Load Unsigned Byte from I/O Peripheral ldbuio rB, IMM16(rA) Not Available in Nios® V processor -
Load Halfword from Memory ldh rB, IMM16(rA) Load Halfword from Memory lh xB, IMM12(xA)
Load Halfword from I/O Peripheral ldhio rB, IMM16(rA) Not Available in Nios® V processor -
Load Unsigned Halfword from Memory ldhu rB, IMM16(rA) Load Unsigned Halfword from Memory lhu xB, IMM12(xA)
Load Unsigned Halfword from I/O Peripheral ldhuio rB, IMM16(rA) Not Available in Nios® V processor -
Load 32-bit Word from Memory ldw rB, IMM16(rA) Load 32-bit Word from Memory lw xB, IMM12(xA)
Load 32-bit Word from I/O Peripheral ldwio rB, IMM16(rA) Not Available in Nios® V processor -
rC ← rA mov rC, rA xC ← xA mv xC, xA
rB ← (IMMED : 0x0000) movhi rB, IMMED xB ← (IMMED: 0x0000)

li xB, IMMED

li xC, 0xffff0000

and xB, xB, xC

rB ← σ(IMMED) movi rB, IMMED

xB ← σ(IMM12)

 addi xB, x0, IMM12
Move Immediate Address into Word movia rB, label

Move Immediate Address into Word

 lla xB, label
rB ← IMMED movui rB, IMMED xB ← IMMED li xB, IMMED
Store Byte to Memory stb rB, IMM16(rA)

Store Byte to Memory

 sb xB, IMM12(xA)
Store Byte to I/O Peripheral stbio rB, IMM16(rA) Not Available in Nios® V processor -
Store Halfword to Memory sth rB, IMM16(rA)

Store Halfword to Memory

 sh xB, IMM12(xA)
Store Halfword to I/O Peripheral sthio rB, IMM16(rA) Not Available in Nios® V processor -
Store 32-bit Word to Memory stw rB, IMM16(rA)

Store 32-bit Word to Memory

 sw xB, IMM12(xA)
Store 32-bit Word to I/O Peripheral stwio rB, IMM16(rA) Not Available in Nios® V processor -
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