AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 5/22/2025
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Shadow Register 6.4. Ethernet Stack 6.5. Bootloader 6.6. Data and Instruction Cache 6.7. Tightly Coupled Memory 6.8. Custom Instructions 6.9. Error Correction Code 6.10. Altera HAL Settings 6.11. Micrium MicroC/OS-II BSP Settings 6.12. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

6.5. Bootloader

Both Nios® II and Nios® V processors support:

  • Execute-in-place (XIP) using alt_load function
  • Program copied to system RAM using boot copier
Table 31.  Supported Flash Memories with Respective Boot Options
Supported Boot Memories Device Nios® V Processor Booting Methods Application Runtime Location Boot Copier
On-Chip Flash (for Internal configuration) MAX® 10 FPGA devices only (with On-Chip Flash IP) Nios® V processor application execute-in-place from On-Chip Flash On-Chip Flash (XIP) + OCRAM/ External RAM (for writable data sections) alt_load() function
Nios® V processor application copied from On-Chip Flash to RAM using boot copier OCRAM/ External RAM Reusing Bootloader via GSFI
General Purpose QSPI Flash (for user data only)

All supported FPGA devices (with Generic Serial Flash Interface FPGA IP)

Nios® V processor application execute-in-place from general purpose QSPI flash General purpose QSPI flash (XIP) + OCRAM/ External RAM (for writable data sections) alt_load() function
Nios® V processor application copied from general purpose QSPI flash to RAM using boot copier OCRAM/ External RAM Bootloader via GSFI
Configuration QSPI Flash (for Active Serial configuration) Control block-based devices (with Generic Serial Flash Interface Altera FPGA IP) 2

Nios® V processor application execute-in-place from configuration QSPI flash.

Configuration QSPI flash (XIP) + OCRAM/ External RAM (for writable data sections) alt_load() function
Nios® V processor application copied from configuration QSPI flash to RAM using boot copier. OCRAM/ External RAM GSFI bootloader
SDM-based devices (with Mailbox Client Altera FPGA IP). 2 Nios® V processor application copied from configuration QSPI flash to RAM using boot copier. OCRAM/ External RAM SDM bootloader

On-chip Memory (OCRAM)

 All supported Altera FPGA devices. 2 Nios® V processor application execute-in-place from OCRAM. OCRAM alt_load() function
Tightly Coupled Memory (TCM) All supported Altera FPGA devices.2 Nios® V processor application execute-in-place from TCM. Instruction TCM (XIP) + Data TCM (for writable data sections) None
2 Refer to AN 980: Nios® V Processor Quartus® Prime Software Support for the device list.
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