AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 5/22/2025
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Shadow Register 6.4. Ethernet Stack 6.5. Bootloader 6.6. Data and Instruction Cache 6.7. Tightly Coupled Memory 6.8. Custom Instructions 6.9. Error Correction Code 6.10. Altera HAL Settings 6.11. Micrium MicroC/OS-II BSP Settings 6.12. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

6.2. Interrupt

Nios® II processor offers Internal (IIC) or External Interrupt Controller (EIC) for interrupt handling, while Nios® V processor provides the Core-Local Interruptor (CLINT) and Core-Local Interrupt Controller (CLIC). The difference results from the Instruction Set Architectures (ISAs) of the processors: Nios® II and RISC-V.
Table 26.  Comparison between Each Interrupt Controller
Implementation Nios® V Processor Nios® II Processor
CLINT-Direct CLINT-Vectored CLIC IIC EIC with Vectored Interrupt Controller
Interrupt type Non-vectored Vectored Non-vectored Non-vectored Vectored
Hardware (Platform) interrupt 16 interrupts 16 to 2048 interrupts 32 interrupts Unlimited
Software interrupt 1 interrupt Not supported Tied to each hardware interrupt.
Timer interrupt 1 interrupt Implement as hardware interrupt with Interval Timer Core.
Pre-emption with interrupt level Not supported Supported Not supported Supported
Priority arbitration Not supported Supported Not supported Supported
Register Set Switching with Shadow Register Supported Not supported Supported
Configurable non-maskable interrupt Implement using the global Machine Interrupt Enable bit in Machine Status Register (mstatus.mie) Not supported Supported
Configurable trigger condition Positive level trigger only
  • Positive level trigger
  • Rising edge trigger
  • Negative level trigger
  • Falling edge trigger
 Positive level trigger only
Legacy HAL Interrupt API Not supported Supported
Enhanced HAL Interrupt API Supported Supported
  • The HAL driver for hardware interrupt is compatible, but take note that the Nios® V processor accepts interrupts number up to 16 only which reflects the difference in interrupt bus width.
  • Altera provides the HAL API for software interrupt and timer interrupt for the Nios® V processor.

If you have custom device drivers, Altera recommends that you upgrade them to use the enhanced HAL interrupt API. The enhanced API maintains compatibility with the IIC. The legacy HAL interrupt API is deprecated. Upgrading your device driver is very simple, requiring only minor changes to some function calls.

Table 27.  HAL Interrupt Legacy and Enhanced API Functions
Legacy API Function Enhanced API Function
alt_irq_register() alt_ic_isr_register()
alt_irq_disable() alt_ic_irq_disable()
alt_irq_enable() alt_ic_irq_enable()
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