Visible to Intel only — GUID: ckk1678178982026
Ixiasoft
5.1. Migrating Nios® II Processor to Nios® V Processor
5.2. Timer
5.3. Interrupt
5.4. Ethernet Stack
5.5. Bootloader
5.6. Data and Instruction Cache
5.7. Tightly Coupled Memory
5.8. Custom Instructions
5.9. Error Correction Code
5.10. Intel® HAL Settings
5.11. Micrium MicroC/OS-II BSP Settings
5.12. Software Packages
Visible to Intel only — GUID: ckk1678178982026
Ixiasoft
5.3. Interrupt
Nios® V processor implements 16 hardware interrupt inputs and internal timer or software interrupts.
Feature | Nios® V Processor | Nios® II Processor |
---|---|---|
Hardware interrupts | 16 interrupts | 32 interrupts |
Software interrupt | Supported | Not supported |
Timer interrupt | Supported | Not supported |
External Interrupt Controller | Not supported | Supported |
Legacy HAL Interrupt API | Not supported | Supported |
Enhanced HAL Interrupt API | Supported | Supported |
- The HAL driver for hardware interrupt is compatible, but take note that the Nios® V processor accepts interrupts number up to 16 only which reflects the difference in interrupt bus width.
- Altera provides the HAL API for software interrupt and timer interrupt for the Nios® V processor.
If you have custom device drivers, Altera recommends that you upgrade them to use the enhanced HAL interrupt API. The enhanced API maintains compatibility with the IIC. The legacy HAL interrupt API is deprecated. Upgrading your device driver is very simple, requiring only minor changes to some function calls.
Legacy API Function | Enhanced API Function |
---|---|
alt_irq_register() | alt_ic_isr_register() |
alt_irq_disable() | alt_ic_irq_disable() |
alt_irq_enable() | alt_ic_irq_enable() |
Related Information