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5.1. Migrating Nios® II Processor to Nios® V Processor
5.2. Timer
5.3. Interrupt
5.4. Ethernet Stack
5.5. Bootloader
5.6. Data and Instruction Cache
5.7. Tightly Coupled Memory
5.8. Custom Instructions
5.9. Error Correction Code
5.10. Intel® HAL Settings
5.11. Micrium MicroC/OS-II BSP Settings
5.12. Software Packages
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5.9. Error Correction Code
All Nios® V processor variant and Nios® II/f processors support ECC (except for Nios® II/e processor).
ECC | Nios® V Processor | Nios® II/f Processor |
---|---|---|
Supported variant |
|
Nios® II/f |
ECC Detection |
|
|
ECC Recovery | — | Available for instruction cache, or any 1-bit ECC errors. |
Output Signals | A conduit group, called cpu_ecc_status. | An Avalon streaming source, called ecc_event_bus. |
Status Reporting |
|
29-bit one-hot encoding representing:
|