AN 978: Nios® V Processor Migration Guidelines

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ID 773196
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Ethernet Stack 6.4. Bootloader 6.5. Data and Instruction Cache 6.6. Tightly Coupled Memory 6.7. Custom Instructions 6.8. Error Correction Code 6.9. Intel® HAL Settings 6.10. Micrium MicroC/OS-II BSP Settings 6.11. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

6.8. Error Correction Code

All Nios® V processor variant and Nios® II/f processors support ECC (except for Nios® II/e processor).
Table 33.  ECC Comparison
ECC Nios® V Processor Nios® II/f Processor
Supported variant
  • Nios® V/m
  • Nios® V/g
  • Nios® V/c
Nios® II/f
ECC Detection
  • 1-bit ECC error
  • 2-bit ECC error
  • 1-bit ECC error
  • 2-bit ECC error
ECC Recovery Available for instruction cache, or any 1-bit ECC errors in Nios® V/g processor only. Available for instruction cache, or any 1-bit ECC errors.
Output Signals A conduit group, called cpu_ecc_status. An Avalon streaming source, called ecc_event_bus.
Status Reporting
  • cpu_ecc_status indicates the error status using 2-bit label encoding.
  • cpu_ecc_sourcecpu_ecc_source indicates the error source using 4-bit label encoding.

29-bit one-hot encoding representing:

  • Affected internal RAM blocks, and
  • Error type.
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