AN 978: Nios® V Processor Migration Guidelines

Download PDF
ID 773196
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Architecture Comparison 3. Processor Core Upgrade Paths 4. Design Flow Comparison 5. Processor Core Comparison 6. Feature Comparison 7. Assembly Language Comparison 8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines
2. Architecture Comparison x
2.1. Features Comparison 2.2. Ecosystem Comparison 2.3. Software Optimization
4. Design Flow Comparison x
4.1. Differences in the Design Flow 4.2. Design Upgrade from Nios® II Processor to Nios® V Processor
4.2. Design Upgrade from Nios® II Processor to Nios® V Processor x
4.2.1. Quartus® Prime Standard Edition 4.2.2. Quartus® Prime Pro Edition
4.2.1. Quartus® Prime Standard Edition x
4.2.1.1. Hardware Component 4.2.1.2. Software Component
4.2.2. Quartus® Prime Pro Edition x
4.2.2.1. Hardware Component 4.2.2.2. Software Component
5. Processor Core Comparison x
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor 5.2. Upgrading Nios® II Processor to Nios® V/m Processor 5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor
5.1. Upgrading Nios® II/e Processor to Nios® V/c Processor x
5.1.1. Hardware Perspective 5.1.2. Software Perspective
5.1.1. Hardware Perspective x
5.1.1.1. Signal and Interface Mapping 5.1.1.2. IP Parameter Configuration 5.1.1.3. BSP Project Generation
5.1.2. Software Perspective x
5.1.2.1. Command-Line Build Flow 5.1.2.2. IDE Build Flow
5.2. Upgrading Nios® II Processor to Nios® V/m Processor x
5.2.1. Hardware Perspective 5.2.2. Software Perspective
5.2.1. Hardware Perspective x
5.2.1.1. Signal and Interface Mapping 5.2.1.2. IP Parameter Configuration 5.2.1.3. BSP Project Generation
5.2.2. Software Perspective x
5.2.2.1. Command-Line Build Flow 5.2.2.2. IDE Build Flow
5.3. Upgrading Nios® II/f Processor to Nios® V/g Processor x
5.3.1. Hardware Perspective 5.3.2. Software Perspective
5.3.1. Hardware Perspective x
5.3.1.1. Signal and Interface Mapping 5.3.1.2. IP Parameter Configuration 5.3.1.3. BSP Project Generation
5.3.2. Software Perspective x
5.3.2.1. Command-Line Build Flow 5.3.2.2. IDE Build Flow
6. Feature Comparison x
6.1. Timer 6.2. Interrupt 6.3. Ethernet Stack 6.4. Bootloader 6.5. Data and Instruction Cache 6.6. Tightly Coupled Memory 6.7. Custom Instructions 6.8. Error Correction Code 6.9. Intel® HAL Settings 6.10. Micrium MicroC/OS-II BSP Settings 6.11. Software Packages
7. Assembly Language Comparison x
7.1. Arithmetic and Logic Operations 7.2. Data Handling and Memory Operations 7.3. Control Flow Operations 7.4. Miscellaneous Operations
1. Overview
2. Architecture Comparison
3. Processor Core Upgrade Paths
4. Design Flow Comparison
5. Processor Core Comparison
6. Feature Comparison
7. Assembly Language Comparison
8. Document Revision History for the AN 978: Nios® V Processor Migration Guidelines

4.2.1.1. Hardware Component

If you compile your design using Quartus® Prime Standard Edition, you can start upgrading to Nios® V processor from Platform Designer. The following figure shows an example of the Nios® II Processor QSYS design.
Figure 1.  Nios® II Processor Qsys Design
  1. From IP Catalog, search for Nios® V processor. Identify your preferred processor core.
  2. Double-click on your selected processor.
  3. The parameters window appears. Select Enable Reset from Debug Module. Click Finish.
  4. The selected processor core is added to your system. Proceed to set the required connections based on the table below:
    Table 7.   Nios® II Processor to Nios® V Processor Interfaces
    Interface Nios® V Processor Nios® II Processor Description
    Clock clock clock Similar clock input
    Reset reset reset Similar hard reset
    Debug reset
    • dbg_reset_out
    • ndm_reset_in
    		 debug_reset_request
    • Mainly used to issue debug reset from CLI or IDE.
    • By default, this feature is enabled in Nios® II/e processor but disabled in Nios® V/m processor.
    Interrupts platform_irq_rx irq
    • Nios® II/e processor supports 32 platform interrupts.
    • Nios® V/m processor supports 16 platform interrupts.
    Timer and Software Interrupt Module timer_sw_agent —
    • Only supported in Nios® V/m and Nios® V/g processors.
    • By default, it is connected to the data manager.
    Debug dm_agent debug_mem_slave
    • Allow JTAG download and debug. For Nios® V/m and Nios® V/g processors, it is connected to the data manager and instruction manager by default.
    • Not applicable to Nios® V/c processor.
    Data bus data_manager data_master
    • Nios® II/e processor uses Avalon® memory-mapped interface.
    • Nios® V/m processor uses Arm* AMBA* AXI-4.
    Instruction bus instruction_manager instruction_master
    • Nios® II/e processor uses Avalon memory-mapped interface.
    • Nios® V/m processor uses Arm AMBA AXI-4.
  5. Open your selected Nios® V processor IP. Click Vectors > Reset Agent and update the parameter as onchip_memory2_0.s1
  6. Remove Nios® II processor from Platform Designer. A preview of the final system is shown as below.
    Figure 2.  Nios® V Processor System
You can now generate the system HDL and compile Quartus® Prime project. Use the Quartus® Prime Programmer software to configure the design SOF file for design verification.
Level Two Title