Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide

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ID 739942
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Quartus® Prime Software and Driver Installation
2.3. Quartus® Prime Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFP NRZ Tab 4.2.5.2. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab
5. Development Kit Hardware and Configuration x
5.1. JTAG Configuration Mode 5.2. Active Serial (AS) x4 Configuration Mode 5.3. Avalon® Streaming Interface x16 Configuration Mode
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. FPGA Configuration A.3. Default Switch and Jumper Settings A.4. Input and Output Components A.5. Components and Interfaces A.6. I2C A.7. MAX® 10 SPI Bus A.8. Clock Circuits A.9. HPS Daughter Card A.10. System Power A.11. Power Guidelines A.12. Power Distribution System A.13. Power Measurement A.14. Thermal Limitations and Protection
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components A.1.3. MAX® 10 CPLD System Controller
A.2. FPGA Configuration x
A.2.1. Programming the FPGA over On-Board Intel® FPGA Download Cable II A.2.2. Programming the FPGA over an External Intel® FPGA Download Cable II
A.3. Default Switch and Jumper Settings x
A.3.1. Switch Description A.3.2. Jumper Description
A.4. Input and Output Components x
A.4.1. Push Buttons A.4.2. Switches A.4.3. LEDs
A.5. Components and Interfaces x
A.5.1. PCI Express* ( PCIe* ) Interface A.5.2. QSFP-DD Interface A.5.3. QSFP Interface A.5.4. CXL Interface A.5.5. DDR4 DIMM1 Interface A.5.6. DDR4 DIMM2 Interface A.5.7. DDR4 Component Interface A.5.8. HPS IO48 Interface
A.11. Power Guidelines x
A.11.1. In a Standard PCIe* -Compliant System A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.3.1. Switch Description

Table 16.  SW1—4 Position DIP for PCIe* Lane Width Selection
Switch Position Board Label Function Default Position
1 x16 ON for PCIe* x16 ON
2 x8 ON for PCIe* x8 OFF
3 x4 ON for PCIe* x4 OFF
4 x1 ON for PCIe* x1 OFF
Table 17.  SW2—Single DIP for Intel® FPGA Download Cable II Selection
Switch Position Board Label Function Default Position
SW2 USB MAX JTAG SEL ON for on-board Intel® FPGA Download Cable II ON
OFF for external Intel® FPGA Download Cable II
Table 18.  SW3—4 position DIP for Configuration Mode Selection and JTAG ControlBy default, MSEL[2:0] is set to '001' for AS x4 with CvP support. MSEL0 is tied to logic high.
Switch Position Board Label Function Default Position
1 MSEL1 Configuration MSEL1 ON
2 MSEL2 Configuration MSEL2 ON
3 BMC JTAG SEL ON Selects On-board Blaster ON
4 HPS JTAG BYPASS OFF Bypass HPS JTAG OFF

The board only supports the following configuration modes.

Table 19.  Supported Configuration Modes MSEL0 is tied to logic high.
Configuration Mode MSEL2 MSEL1 MSEL0
JTAG 1 1 1
Avalon® -ST x16 1 0 1
AS x4 Fast (CVP support) 0 0 1
AS x4 Normal 0 1 1
Table 20.  SW4
Switch Position Board Label Function Default Position
1 SSEN ON enables PCIe* Spread Spectrum OFF
2 CXL REFCLK Select OFF for local PCIe* REFCLK on Bank12C OFF
3 PCIe* REFCLK Select OFF for local PCIe* REFCLK on Bank13A OFF
4 PCIe* Clock Power-down ON powers down PCIe* clock sources OFF
Table 21.  SW5—Slide Switch to Power On the Board
Switch position Board Label Function Default Position
SW5 Power On ON to power on the board OFF
Table 22.  SW6—Single DIP for MAX® 10 JTAG Enable
Switch position Board Label Function Default Position
SW6 MAX® 10 JTAG Enable ON to share MAX® 10 JTAG Pins OFF
Table 23.  S[1–4, 6]—Various Push-Button RESET Switches
Switch Function
S1 Used to send RESET to CPU
S2 Used to send RESET to HPS
S3 Used to send PERSTN to PCIe*
S4 Used to send 2nd PERSTN to PCIe*
S6 Used to send PERSTN to CXL PCIe*
Level Two Title