Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide

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ID 739942
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Quartus® Prime Software and Driver Installation
2.3. Quartus® Prime Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFP NRZ Tab 4.2.5.2. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab
5. Development Kit Hardware and Configuration x
5.1. JTAG Configuration Mode 5.2. Active Serial (AS) x4 Configuration Mode 5.3. Avalon® Streaming Interface x16 Configuration Mode
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. FPGA Configuration A.3. Default Switch and Jumper Settings A.4. Input and Output Components A.5. Components and Interfaces A.6. I2C A.7. MAX® 10 SPI Bus A.8. Clock Circuits A.9. HPS Daughter Card A.10. System Power A.11. Power Guidelines A.12. Power Distribution System A.13. Power Measurement A.14. Thermal Limitations and Protection
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components A.1.3. MAX® 10 CPLD System Controller
A.2. FPGA Configuration x
A.2.1. Programming the FPGA over On-Board Intel® FPGA Download Cable II A.2.2. Programming the FPGA over an External Intel® FPGA Download Cable II
A.3. Default Switch and Jumper Settings x
A.3.1. Switch Description A.3.2. Jumper Description
A.4. Input and Output Components x
A.4.1. Push Buttons A.4.2. Switches A.4.3. LEDs
A.5. Components and Interfaces x
A.5.1. PCI Express* ( PCIe* ) Interface A.5.2. QSFP-DD Interface A.5.3. QSFP Interface A.5.4. CXL Interface A.5.5. DDR4 DIMM1 Interface A.5.6. DDR4 DIMM2 Interface A.5.7. DDR4 Component Interface A.5.8. HPS IO48 Interface
A.11. Power Guidelines x
A.11.1. In a Standard PCIe* -Compliant System A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.8. Clock Circuits

Figure 30.  Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit Clocks and Default Frequencies
Table 39.  On-Board Oscillators Sources for the FPGA
Source Schematic Signal Name Frequency (MHz) I/O Standard Agilex™ 7 Pin Number (P/N) Application
U23 TOD_MASTER_CLK_125M_P/N 125 Differential G43/F44 IEEE 1588 TOD master clock
CLK_FPGA_100M_P/N 100 LVDS CK18/CL19 General-purpose FPGA clock
PTP_SAMPLE_CLK_250M_P/N 250 Differential E45/D46 IEEE 1588 PTP clock
DDR4_DIMM1_REFCLK_P/N 166.625 LVDS CV28/CW29 DDR4 DIMM1 clock
DDR4_DIMM2_REFCLK_P/N 166.625 LVDS DD36/DC37 DDR4 DIMM2 clock
DDR4_COMP_REFCLK_P/N 166.625 LVDS U5/T6 DDR4 component clock
QSFP_REFCLK_P/N 156.25 Differential AW49/AV48 QSFP clock
QSFPDD_REFCLK_P/N 156.25 Differential AD48/AC49 QSFPDD clock
CIPRI_HIGH_REFCLK_P/N 184.32 Differential AJ48/AH49 CIPRI high clock
CIPRI_LOW_REFCLK_P/N 153.6 Differential AR49/AU49 CIPRI low clock
U27 REFCLK_CXL_CONN_P/N 100 HCSL BG49/BF48 PCIe* REFCLK bank 12C channel 1
REFCLK_CXL_EP_P/N 100 HCSL BC49/BE49 PCIe* REFCLK bank 12C channel 0
U26 REFCLK_PCIE_13A_CH2_P/N 100 HCSL BR7/BU7 PCIe* REFCLK bank 13A channel 2
REFCLK_PCIE_13A_CH5_P/N 100 HCSL CD8/CC7 PCIe* REFCLK bank 13A channel 5
U10 FPGA_OSC_CLK1 125 1.8 V LVCMOS CB42 Configuration clock
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