Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide

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ID 739942
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Quartus® Prime Software and Driver Installation
2.3. Quartus® Prime Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFP NRZ Tab 4.2.5.2. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab
5. Development Kit Hardware and Configuration x
5.1. JTAG Configuration Mode 5.2. Active Serial (AS) x4 Configuration Mode 5.3. Avalon® Streaming Interface x16 Configuration Mode
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. FPGA Configuration A.3. Default Switch and Jumper Settings A.4. Input and Output Components A.5. Components and Interfaces A.6. I2C A.7. MAX® 10 SPI Bus A.8. Clock Circuits A.9. HPS Daughter Card A.10. System Power A.11. Power Guidelines A.12. Power Distribution System A.13. Power Measurement A.14. Thermal Limitations and Protection
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components A.1.3. MAX® 10 CPLD System Controller
A.2. FPGA Configuration x
A.2.1. Programming the FPGA over On-Board Intel® FPGA Download Cable II A.2.2. Programming the FPGA over an External Intel® FPGA Download Cable II
A.3. Default Switch and Jumper Settings x
A.3.1. Switch Description A.3.2. Jumper Description
A.4. Input and Output Components x
A.4.1. Push Buttons A.4.2. Switches A.4.3. LEDs
A.5. Components and Interfaces x
A.5.1. PCI Express* ( PCIe* ) Interface A.5.2. QSFP-DD Interface A.5.3. QSFP Interface A.5.4. CXL Interface A.5.5. DDR4 DIMM1 Interface A.5.6. DDR4 DIMM2 Interface A.5.7. DDR4 Component Interface A.5.8. HPS IO48 Interface
A.11. Power Guidelines x
A.11.1. In a Standard PCIe* -Compliant System A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.5.6. DDR4 DIMM2 Interface

The Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit board provides two DDR4 x72 DIMM interfaces connected to the FPGA fabric. DIMM2 is connected to the Agilex™ 7 IO96 of banks 2E and 2F. Only one DIMM memory module is included with the development kit for evaluation of the DIMM interfaces.
Note: DIMM2 (J5) is not available in the Agilex™ 7 AGFD023R24C2E1VC development kit.
Table 33.  DIMM2 Pin AssignmentsNot available in the Agilex™ 7 AGFD023R24C2E1VC development kit.
Schematic Signal Name FPGA Pin Number I/O Standard Description
DDR4_DIMM2_DQ0 CK46 1.2 V HS LVCMOS DDR4 DIMM2 DQ0 data
DDR4_DIMM2_DQ1 CL47 1.2 V HS LVCMOS DDR4 DIMM2 DQ1 data
DDR4_DIMM2_DQ2 CN47 1.2 V HS LVCMOS DDR4 DIMM2 DQ2 data
DDR4_DIMM2_DQ3 CP46 1.2 V HS LVCMOS DDR4 DIMM2 DQ3 data
DDR4_DIMM2_DQ4 CL43 1.2 V HS LVCMOS DDR4 DIMM2 DQ4 data
DDR4_DIMM2_DQ5 CK42 1.2 V HS LVCMOS DDR4 DIMM2 DQ5 data
DDR4_DIMM2_DQ6 CN43 1.2 V HS LVCMOS DDR4 DIMM2 DQ6 data
DDR4_DIMM2_DQ7 CP42 1.2 V HS LVCMOS DDR4 DIMM2 DQ7 data
DDR4_DIMM2_DQS_P0 CP44 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 0
DDR4_DIMM2_DQS_N0 CN45 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 0
DDR4_DIMM2_DBI_N0 CK44 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 0
DDR4_DIMM2_TDQS_N9 CL45 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 0
DDR4_DIMM2_DQ8 DA45 1.2 V HS LVCMOS DDR4 DIMM2 DQ8 data
DDR4_DIMM2_DQ9 DC45 1.2 V HS LVCMOS DDR4 DIMM2 DQ9 data
DDR4_DIMM2_DQ10 DD44 1.2 V HS LVCMOS DDR4 DIMM2 DQ10 data
DDR4_DIMM2_DQ11 CY44 1.2 V HS LVCMOS DDR4 DIMM2 DQ11 data
DDR4_DIMM2_DQ12 DA49 1.2 V HS LVCMOS DDR4 DIMM2 DQ12 data
DDR4_DIMM2_DQ13 CY48 1.2 V HS LVCMOS DDR4 DIMM2 DQ13 data
DDR4_DIMM2_DQ14 DD48 1.2 V HS LVCMOS DDR4 DIMM2 DQ14 data
DDR4_DIMM2_DQ15 DC49 1.2 V HS LVCMOS DDR4 DIMM2 DQ15 data
DDR4_DIMM2_DQS_P1 DD46 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 1
DDR4_DIMM2_DQS_N1 DC47 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 1
DDR4_DIMM2_DBI_N1 CY46 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 1
DDR4_DIMM2_TDQS_N10 DA47 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 1
DDR4_DIMM2_DQ16 CN49 1.2 V HS LVCMOS DDR4 DIMM2 DQ16 data
DDR4_DIMM2_DQ17 CP48 1.2 V HS LVCMOS DDR4 DIMM2 DQ17 data
DDR4_DIMM2_DQ18 CL49 1.2 V HS LVCMOS DDR4 DIMM2 DQ18 data
DDR4_DIMM2_DQ19 CK48 1.2 V HS LVCMOS DDR4 DIMM2 D19 data
DDR4_DIMM2_DQ20 CM52 1.2 V HS LVCMOS DDR4 DIMM2 DQ20 data
DDR4_DIMM2_DQ21 CT52 1.2 V HS LVCMOS DDR4 DIMM2 DQ21 data
DDR4_DIMM2_DQ22 CN53 1.2 V HS LVCMOS DDR4 DIMM2 DQ22 data
DDR4_DIMM2_DQ23 CR53 1.2 V HS LVCMOS DDR4 DIMM2 DQ23 data
DDR4_DIMM2_DQS_P2 CP50 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 2
DDR4_DIMM2_DQS_N2 CN51 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 2
DDR4_DIMM2_DBI_N2 CK50 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 2
DDR4_DIMM2_TDQS_N11 CL51 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 2
DDR4_DIMM2_DQ24 CR47 1.2 V HS LVCMOS DDR4 DIMM2 DQ24 data
DDR4_DIMM2_DQ25 CT46 1.2 V HS LVCMOS DDR4 DIMM2 DQ25 data
DDR4_DIMM2_DQ26 CV46 1.2 V HS LVCMOS DDR4 DIMM2 DQ26 data
DDR4_DIMM2_DQ27 CW47 1.2 V HS LVCMOS DDR4 DIMM2 DQ27 data
DDR4_DIMM2_DQ28 CW43 1.2 V HS LVCMOS DDR4 DIMM2 DQ28 data
DDR4_DIMM2_DQ29 CV42 1.2 V HS LVCMOS DDR4 DIMM2 DQ29 data
DDR4_DIMM2_DQ30 CR43 1.2 V HS LVCMOS DDR4 DIMM2 DQ30 data
DDR4_DIMM2_DQ31 CT42 1.2 V HS LVCMOS DDR4 DIMM2 DQ31 data
DDR4_DIMM2_DQS_P3 CV44 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 3
DDR4_DIMM2_DQS_N3 CW45 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 3
DDR4_DIMM2_DBI_N3 CT44 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 3
DDR4_DIMM2_TDQS_N12 CR45 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 3
DDR4_DIMM2_DQ32 CV48 1.2 V HS LVCMOS DDR4 DIMM2 DQ32 data
DDR4_DIMM2_DQ33 CT48 1.2 V HS LVCMOS DDR4 DIMM2 DQ33 data
DDR4_DIMM2_DQ34 CW49 1.2 V HS LVCMOS DDR4 DIMM2 DQ34 data
DDR4_DIMM2_DQ35 CR49 1.2 V HS LVCMOS DDR4 DIMM2 DQ35 data
DDR4_DIMM2_DQ36 CW53 1.2 V HS LVCMOS DDR4 DIMM2 DQ36 data
DDR4_DIMM2_DQ37 CV52 1.2 V HS LVCMOS DDR4 DIMM2 DQ37 data
DDR4_DIMM2_DQ38 CW55 1.2 V HS LVCMOS DDR4 DIMM2 DQ38 data
DDR4_DIMM2_DQ39 CV54 1.2 V HS LVCMOS DDR4 DIMM2 DQ39 data
DDR4_DIMM2_DQS_P4 CV50 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 4
DDR4_DIMM2_DQS_N4 CW51 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 4
DDR4_DIMM2_DBI_N4 CT50 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 4
DDR4_DIMM2_TDQS_N13 CR51 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 4
DDR4_DIMM2_DQ40 CY50 1.2 V HS LVCMOS DDR4 DIMM2 DQ40 data
DDR4_DIMM2_DQ41 DC51 1.2 V HS LVCMOS DDR4 DIMM2 DQ41 data
DDR4_DIMM2_DQ42 DA51 1.2 V HS LVCMOS DDR4 DIMM2 DQ42 data
DDR4_DIMM2_DQ43 DD50 1.2 V HS LVCMOS DDR4 DIMM2 DQ43 data
DDR4_DIMM2_DQ44 CY54 1.2 V HS LVCMOS DDR4 DIMM2 DQ44 data
DDR4_DIMM2_DQ45 DA55 1.2 V HS LVCMOS DDR4 DIMM2 DQ45 data
DDR4_DIMM2_DQ46 DD54 1.2 V HS LVCMOS DDR4 DIMM2 DQ46 data
DDR4_DIMM2_DQ47 DC55 1.2 V HS LVCMOS DDR4 DIMM2 DQ47 data
DDR4_DIMM2_DQS_P5 DD52 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 5
DDR4_DIMM2_DQS_N5 DC52 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 5
DDR4_DIMM2_DBI_N5 CY52 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 5
DDR4_DIMM2_TDQS_N14 DA53 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 5
DDR4_DIMM2_DQ48 CL41 1.2 V HS LVCMOS DDR4 DIMM2 DQ48 data
DDR4_DIMM2_DQ49 CN41 1.2 V HS LVCMOS DDR4 DIMM2 DQ49 data
DDR4_DIMM2_DQ50 CK40 1.2 V HS LVCMOS DDR4 DIMM2 DQ50 data
DDR4_DIMM2_DQ51 CP40 1.2 V HS LVCMOS DDR4 DIMM2 DQ51 data
DDR4_DIMM2_DQ52 CK36 1.2 V HS LVCMOS DDR4 DIMM2 DQ52 data
DDR4_DIMM2_DQ53 CN37 1.2 V HS LVCMOS DDR4 DIMM2 DQ53 data
DDR4_DIMM2_DQ54 CL37 1.2 V HS LVCMOS DDR4 DIMM2 DQ54 data
DDR4_DIMM2_DQ55 CP36 1.2 V HS LVCMOS DDR4 DIMM2 DQ55 data
DDR4_DIMM2_DQS_P6 CP38 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 6
DDR4_DIMM2_DQS_N6 CN39 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 6
DDR4_DIMM2_DBI_N6 CK38 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 6
DDR4_DIMM2_TDQS_N15 CL39 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 6
DDR4_DIMM2_DQ56 DF46 1.2 V HS LVCMOS DDR4 DIMM2 DQ56 data
DDR4_DIMM2_DQ57 DE47 1.2 V HS LVCMOS DDR4 DIMM2 DQ57 data
DDR4_DIMM2_DQ58 DH46 1.2 V HS LVCMOS DDR4 DIMM2 DQ58 data
DDR4_DIMM2_DQ59 DJ47 1.2 V HS LVCMOS DDR4 DIMM2 DQ59 data
DDR4_DIMM2_DQ60 DE53 1.2 V HS LVCMOS DDR4 DIMM2 DQ60 data
DDR4_DIMM2_DQ61 DF52 1.2 V HS LVCMOS DDR4 DIMM2 DQ61 data
DDR4_DIMM2_DQ62 DG51 1.2 V HS LVCMOS DDR4 DIMM2 DQ62 data
DDR4_DIMM2_DQ63 DH50 1.2 V HS LVCMOS DDR4 DIMM2 DQ63 data
DDR4_DIMM2_DQS_P7 DH48 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 7
DDR4_DIMM2_DQS_N7 DJ49 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 7
DDR4_DIMM2_DBI_N7 DF48 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 7
DDR4_DIMM2_TDQS_N16 DE49 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 7
DDR4_DIMM2_DQ64 CW41 1.2 V HS LVCMOS DDR4 DIMM2 DQ64 data
DDR4_DIMM2_DQ65 CV40 1.2 V HS LVCMOS DDR4 DIMM2 DQ65 data
DDR4_DIMM2_DQ66 CR41 1.2 V HS LVCMOS DDR4 DIMM2 DQ66 data
DDR4_DIMM2_DQ67 CT40 1.2 V HS LVCMOS DDR4 DIMM2 DQ67 data
DDR4_DIMM2_DQ68 CR37 1.2 V HS LVCMOS DDR4 DIMM2 DQ68 data
DDR4_DIMM2_DQ69 CV36 1.2 V HS LVCMOS DDR4 DIMM2 DQ69 data
DDR4_DIMM2_DQ70 CW37 1.2 V HS LVCMOS DDR4 DIMM2 DQ70 data
DDR4_DIMM2_DQ71 CT36 1.2 V HS LVCMOS DDR4 DIMM2 DQ71 data
DDR4_DIMM2_DQS_P8 CV38 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Positive for byte lane 8
DDR4_DIMM2_DQS_N8 CW39 1.2 V HS LVCMOS DDR4 DIMM2 Data Strobe
Negative for byte lane 8
DDR4_DIMM2_DBI_N8 CT38 1.2 V HS LVCMOS DDR4 DIMM2 Data Bus Inversion for byte lane 8
DDR4_DIMM2_TDQS_N17 CR39 1.2 V HS LVCMOS DDR4 DIMM2 Termination Data Strobe for byte lane 8
DDR4_DIMM2_C1 DJ33 1.2 V HS LVCMOS DDR4 DIMM2 Stacked Device Chip ID 1
DDR4_DIMM2_C0 DH32 1.2 V HS LVCMOS DDR4 DIMM2 Stacked Device Chip ID 0
DDR4_DIMM2_BG0 DA33 1.2 V HS LVCMOS DDR4 DIMM2 Bank Group 0
DDR4_DIMM2_BA1 CY32 1.2 V HS LVCMOS DDR4 DIMM2 Bank Address 1
DDR4_DIMM2_BA0 DC33 1.2 V HS LVCMOS DDR4 DIMM2 Bank Address 0
DDR4_DIMM2_A17 DD32 1.2 V HS LVCMOS DDR4 DIMM2 Address 17
DDR4_DIMM2_A16 DA35 1.2 V HS LVCMOS DDR4 DIMM2 Address 16
DDR4_DIMM2_A15 CY34 1.2 V HS LVCMOS DDR4 DIMM2 Address 15
DDR4_DIMM2_A14 DC35 1.2 V HS LVCMOS DDR4 DIMM2 Address 14
DDR4_DIMM2_A13 DD34 1.2 V HS LVCMOS DDR4 DIMM2 Address 13
DDR4_DIMM2_A12 DA37 1.2 V HS LVCMOS DDR4 DIMM2 Address 12
DDR4_DIMM2_A11 DE35 1.2 V HS LVCMOS DDR4 DIMM2 Address 11
DDR4_DIMM2_A10 DF34 1.2 V HS LVCMOS DDR4 DIMM2 Address 10
DDR4_DIMM2_A9 DJ35 1.2 V HS LVCMOS DDR4 DIMM2 Address 9
DDR4_DIMM2_A8 DH34 1.2 V HS LVCMOS DDR4 DIMM2 Address 8
DDR4_DIMM2_A7 DE37 1.2 V HS LVCMOS DDR4 DIMM2 Address 7
DDR4_DIMM2_A6 DF36 1.2 V HS LVCMOS DDR4 DIMM2 Address 6
DDR4_DIMM2_A5 DJ37 1.2 V HS LVCMOS DDR4 DIMM2 Address 5
DDR4_DIMM2_A4 DH36 1.2 V HS LVCMOS DDR4 DIMM2 Address 4
DDR4_DIMM2_A3 DE39 1.2 V HS LVCMOS DDR4 DIMM2 Address 3
DDR4_DIMM2_A2 DF38 1.2 V HS LVCMOS DDR4 DIMM2 Address 2
DDR4_DIMM2_A1 DJ39 1.2 V HS LVCMOS DDR4 DIMM2 Address 1
DDR4_DIMM2_A0 DH38 1.2 V HS LVCMOS DDR4 DIMM2 Address 0
DDR4_DIMM2_PAR DA39 1.2 V HS LVCMOS DDR4 DIMM2 Parity
DDR4_DIMM2_CS_N1 CY38 1.2 V HS LVCMOS DDR4 DIMM2 Chip Select 1
DDR4_DIMM2_CK_N0 DC39 1.2 V HS LVCMOS DDR4 DIMM2 Clock 0,
Positive
DDR4_DIMM2_CK_P0 DD38 1.2 V HS LVCMOS DDR4 DIMM2 Clock 0,
Negative
DDR4_DIMM2_CKE1 DA41 1.2 V HS LVCMOS DDR4 DIMM2 Clock Enable 1
DDR4_DIMM2_CKE0 DD40 1.2 V HS LVCMOS DDR4 DIMM2 Clock Enable 0
DDR4_DIMM2_ODT1 DC41 1.2 V HS LVCMOS DDR4 DIMM2 On Die Termination 1
DDR4_DIMM2_ODT0 DD40 1.2 V HS LVCMOS DDR4 DIMM2 On Die Termination 0
DDR4_DIMM2_ACT_N DA43 1.2 V HS LVCMOS DDR4 DIMM2 Activate Command
DDR4_DIMM2_CS_N0 CY42 1.2 V HS LVCMOS DDR4 DIMM2 Chip Select 0
DDR4_DIMM2_RESET_N DC43 1.2 V HS LVCMOS DDR4 DIMM2 Reset
DDR4_DIMM2_BG1 DD42 1.2 V HS LVCMOS DDR4 DIMM2 Bank Group 1
Level Two Title