Visible to Intel only — GUID: lgq1660806356241
Ixiasoft
A.1. Board Overview and Components
A.2. FPGA Configuration
A.3. Default Switch and Jumper Settings
A.4. Input and Output Components
A.5. Components and Interfaces
A.6. I2C
A.7. Intel® MAX® 10 SPI Bus
A.8. Clock Circuits
A.9. HPS Daughter Card
A.10. System Power
A.11. Power Guidelines
A.12. Power Distribution System
A.13. Power Measurement
A.14. Thermal Limitations and Protection
Visible to Intel only — GUID: lgq1660806356241
Ixiasoft
A.6. I2C
The Intel® MAX® 10 and Intel Agilex® 7 devices use the I2C for reading and writing to the various components on the board such as programmable clock generators, voltage regulators, temperature sensors, and EEPROMs. You can use the Intel Agilex® 7 or Intel® MAX® 10 as the I2C host to access these devices, change clock frequencies, or get board status information such as the voltage and temperature readings.
Figure 25. I2C Block Diagram
Schematic Signal Name | MAX Pin Number | I/O Standard | Description |
---|---|---|---|
MAX_I2C_SCL | J11 | 3.3 V open drain | Intel® MAX® 10 I2C clock |
MAX_I2C_SDA | J12 | 3.3 V open drain | Intel® MAX® 10 I2C data |
FX2_SCL | R1 | 3.3 V open drain | USB PHY I2C clock |
FX2_SDA | R3 | 3.3 V open drain | USB PHY I2C data |
Schematic Signal Name | FPGA Pin Number | I/O Standard | Description |
---|---|---|---|
FPGA_1V8_SVID_SCL | CG47 | 1.8 V open drain | Serial voltage ID I2C clock |
FPGA_1V8_SVID_SDA | CB46 | 1.8 V open drain | Serial voltage ID I2C data |
FPGA_1V2_SCL | K44 | 1.2 V open drain | FPGA I2C clock for DDR4 DIMMs, QSFP, QSFPDD, IO expander, and certificate EEPROM |
FPGA_1V2_SDA | J43 | 1.2 V open drain | FPGA I2C data for DDR4 DIMMs, QSFP, QSFPDD, IO expander, and certificate EEPROM |
HPS_SCL | N3 | 1.8 V open drain | HPS I/O48 daughter card I2C clock |
HPS_SDA | L6 | 1.8 V open drain | HPS I/O48 daughter card I2C data |