Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide

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ID 739942
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Quartus® Prime Software and Driver Installation
2.3. Quartus® Prime Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFP NRZ Tab 4.2.5.2. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab
5. Development Kit Hardware and Configuration x
5.1. JTAG Configuration Mode 5.2. Active Serial (AS) x4 Configuration Mode 5.3. Avalon® Streaming Interface x16 Configuration Mode
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. FPGA Configuration A.3. Default Switch and Jumper Settings A.4. Input and Output Components A.5. Components and Interfaces A.6. I2C A.7. MAX® 10 SPI Bus A.8. Clock Circuits A.9. HPS Daughter Card A.10. System Power A.11. Power Guidelines A.12. Power Distribution System A.13. Power Measurement A.14. Thermal Limitations and Protection
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components A.1.3. MAX® 10 CPLD System Controller
A.2. FPGA Configuration x
A.2.1. Programming the FPGA over On-Board Intel® FPGA Download Cable II A.2.2. Programming the FPGA over an External Intel® FPGA Download Cable II
A.3. Default Switch and Jumper Settings x
A.3.1. Switch Description A.3.2. Jumper Description
A.4. Input and Output Components x
A.4.1. Push Buttons A.4.2. Switches A.4.3. LEDs
A.5. Components and Interfaces x
A.5.1. PCI Express* ( PCIe* ) Interface A.5.2. QSFP-DD Interface A.5.3. QSFP Interface A.5.4. CXL Interface A.5.5. DDR4 DIMM1 Interface A.5.6. DDR4 DIMM2 Interface A.5.7. DDR4 Component Interface A.5.8. HPS IO48 Interface
A.11. Power Guidelines x
A.11.1. In a Standard PCIe* -Compliant System A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.5.5. DDR4 DIMM1 Interface

The Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit board provides two DDR4 x72 DIMM interfaces connected to the FPGA fabric. DIMM1 is connected to the Agilex™ 7 IO96 of banks 2C and 2D. Only one DIMM memory module is included with the development kit for evaluation of the DDR4 interfaces.
Table 32.  DIMM1 Pin Assignments
Schematic Signal Name FPGA Pin Number I/O Standard Description
DDR4_DIMM1_DQ0 DC31 1.2 V HS LVCMOS DDR4 DIMM1 DQ0 data
DDR4_DIMM1_DQ1 DD30 1.2 V HS LVCMOS DDR4 DIMM1 DQ1 data
DDR4_DIMM1_DQ2 CY30 1.2 V HS LVCMOS DDR4 DIMM1 DQ2 data
DDR4_DIMM1_DQ3 DA31 1.2 V HS LVCMOS DDR4 DIMM1 DQ3 data
DDR4_DIMM1_DQ4 DA27 1.2 V HS LVCMOS DDR4 DIMM1 DQ4 data
DDR4_DIMM1_DQ5 CY26 1.2 V HS LVCMOS DDR4 DIMM1 DQ5 data
DDR4_DIMM1_DQ6 DC27 1.2 V HS LVCMOS DDR4 DIMM1 DQ6 data
DDR4_DIMM1_DQ7 DD26 1.2 V HS LVCMOS DDR4 DIMM1 DQ7 data
DDR4_DIMM1_DQS_P0 DD28 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 0
DDR4_DIMM1_DQS_N0 DC29 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 0
DDR4_DIMM1_DBI_N0 CY28 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 0
DDR4_DIMM1_TDQS_N9 DA29 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe for byte lane 0
DDR4_DIMM1_DQ8 DF20 1.2 V HS LVCMOS DDR4 DIMM1 DQ8 data
DDR4_DIMM1_DQ9 DJ21 1.2 V HS LVCMOS DDR4 DIMM1 DQ9 data
DDR4_DIMM1_DQ10 DH20 1.2 V HS LVCMOS DDR4 DIMM1 DQ10 data
DDR4_DIMM1_DQ11 DE21 1.2 V HS LVCMOS DDR4 DIMM1 DQ11 data
DDR4_DIMM1_DQ12 DF16 1.2 V HS LVCMOS DDR4 DIMM1 DQ12 data
DDR4_DIMM1_DQ13 DH16 1.2 V HS LVCMOS DDR4 DIMM1 DQ13 data
DDR4_DIMM1_DQ14 DE17 1.2 V HS LVCMOS DDR4 DIMM1 DQ14 data
DDR4_DIMM1_DQ15 DJ17 1.2 V HS LVCMOS DDR4 DIMM1 DQ15 data
DDR4_DIMM1_DQS_P1 DH18 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 1
DDR4_DIMM1_DQS_N1 DJ19 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 1
DDR4_DIMM1_DBI_N1 DF18 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 1
DDR4_DIMM1_TDQS_N10 DE19 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe for byte lane 1
DDR4_DIMM1_DQ16 DF8 1.2 V HS LVCMOS DDR4 DIMM1 DQ16 data
DDR4_DIMM1_DQ17 DH8 1.2 V HS LVCMOS DDR4 DIMM1 DQ17 data
DDR4_DIMM1_DQ18 DE9 1.2 V HS LVCMOS DDR4 DIMM1 DQ18 data
DDR4_DIMM1_DQ19 DJ9 1.2 V HS LVCMOS DDR4 DIMM1 D19 data
DDR4_DIMM1_DQ20 DF2 1.2 V HS LVCMOS DDR4 DIMM1 DQ20 data
DDR4_DIMM1_DQ21 DE3 1.2 V HS LVCMOS DDR4 DIMM1 DQ21 data
DDR4_DIMM1_DQ22 DF4 1.2 V HS LVCMOS DDR4 DIMM1 DQ22 data
DDR4_DIMM1_DQ23 DE5 1.2 V HS LVCMOS DDR4 DIMM1 DQ23 data
DDR4_DIMM1_DQS_P2 DH6 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 2
DDR4_DIMM1_DQS_N2 DJ7 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 2
DDR4_DIMM1_DBI_N2 DF6 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 2
DDR4_DIMM1_TDQS_N11 DE7 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe for byte lane 2
DDR4_DIMM1_DQ24 DE15 1.2 V HS LVCMOS DDR4 DIMM1 DQ24 data
DDR4_DIMM1_DQ25 DF14 1.2 V HS LVCMOS DDR4 DIMM1 DQ25 data
DDR4_DIMM1_DQ26 DJ15 1.2 V HS LVCMOS DDR4 DIMM1 DQ26 data
DDR4_DIMM1_DQ27 DH14 1.2 V HS LVCMOS DDR4 DIMM1 DQ27 data
DDR4_DIMM1_DQ28 DF10 1.2 V HS LVCMOS DDR4 DIMM1 DQ28 data
DDR4_DIMM1_DQ29 DH10 1.2 V HS LVCMOS DDR4 DIMM1 DQ29 data
DDR4_DIMM1_DQ30 DJ11 1.2 V HS LVCMOS DDR4 DIMM1 DQ30 data
DDR4_DIMM1_DQ31 DE11 1.2 V HS LVCMOS DDR4 DIMM1 DQ31 data
DDR4_DIMM1_DQS_P3 DH12 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 3
DDR4_DIMM1_DQS_N3 DJ13 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 3
DDR4_DIMM1_DBI_N3 DF12 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 3
DDR4_DIMM1_TDQS_N12 DE13 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe for byte lane 3
DDR4_DIMM1_DQ32 DH26 1.2 V HS LVCMOS DDR4 DIMM1 DQ32 data
DDR4_DIMM1_DQ33 DE27 1.2 V HS LVCMOS DDR4 DIMM1 DQ33 data
DDR4_DIMM1_DQ34 DF26 1.2 V HS LVCMOS DDR4 DIMM1 DQ34 data
DDR4_DIMM1_DQ35 DJ27 1.2 V HS LVCMOS DDR4 DIMM1 DQ35 data
DDR4_DIMM1_DQ36 DE23 1.2 V HS LVCMOS DDR4 DIMM1 DQ36 data
DDR4_DIMM1_DQ37 DF22 1.2 V HS LVCMOS DDR4 DIMM1 DQ37 data
DDR4_DIMM1_DQ38 DJ23 1.2 V HS LVCMOS DDR4 DIMM1 DQ38 data
DDR4_DIMM1_DQ39 DH22 1.2 V HS LVCMOS DDR4 DIMM1 DQ39 data
DDR4_DIMM1_DQS_P4 DH24 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 4
DDR4_DIMM1_DQS_N4 DJ25 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 4
DDR4_DIMM1_DBI_N4 DF24 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 4
DDR4_DIMM1_TDQS_N13 DE25 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe for byte lane 4
DDR4_DIMM1_DQ40 DC19 1.2 V HS LVCMOS DDR4 DIMM1 DQ40 data
DDR4_DIMM1_DQ41 DD18 1.2 V HS LVCMOS DDR4 DIMM1 DQ41 data
DDR4_DIMM1_DQ42 CY18 1.2 V HS LVCMOS DDR4 DIMM1 DQ42 data
DDR4_DIMM1_DQ43 DA19 1.2 V HS LVCMOS DDR4 DIMM1 DQ43 data
DDR4_DIMM1_DQ44 CY14 1.2 V HS LVCMOS DDR4 DIMM1 DQ44 data
DDR4_DIMM1_DQ45 DA15 1.2 V HS LVCMOS DDR4 DIMM1 DQ45 data
DDR4_DIMM1_DQ46 DC15 1.2 V HS LVCMOS DDR4 DIMM1 DQ46 data
DDR4_DIMM1_DQ47 DD14 1.2 V HS LVCMOS DDR4 DIMM1 DQ47 data
DDR4_DIMM1_DQS_P5 DD16 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 5
DDR4_DIMM1_DQS_N5 DC17 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 5
DDR4_DIMM1_DBI_N5 CY16 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 5
DDR4_DIMM1_TDQS_N14 DA17 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe for byte lane 5
DDR4_DIMM1_DQ48 CY24 1.2 V HS LVCMOS DDR4 DIMM1 DQ48 data
DDR4_DIMM1_DQ49 DD24 1.2 V HS LVCMOS DDR4 DIMM1 DQ49 data
DDR4_DIMM1_DQ50 DC25 1.2 V HS LVCMOS DDR4 DIMM1 DQ50 data
DDR4_DIMM1_DQ51 DA25 1.2 V HS LVCMOS DDR4 DIMM1 DQ51 data
DDR4_DIMM1_DQ52 CY20 1.2 V HS LVCMOS DDR4 DIMM1 DQ52 data
DDR4_DIMM1_DQ53 DC21 1.2 V HS LVCMOS DDR4 DIMM1 DQ53 data
DDR4_DIMM1_DQ54 DA21 1.2 V HS LVCMOS DDR4 DIMM1 DQ54 data
DDR4_DIMM1_DQ55 DD20 1.2 V HS LVCMOS DDR4 DIMM1 DQ55 data
DDR4_DIMM1_DQS_P6 DD22 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 6
DDR4_DIMM1_DQS_N6 DC23 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 6
DDR4_DIMM1_DBI_N6 CY22 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 6
DDR4_DIMM1_TDQS_N15 DA23 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe for byte lane 6
DDR4_DIMM1_DQ56 CY12 1.2 V HS LVCMOS DDR4 DIMM1 DQ56 data
DDR4_DIMM1_DQ57 DC13 1.2 V HS LVCMOS DDR4 DIMM1 DQ57 data
DDR4_DIMM1_DQ58 DA13 1.2 V HS LVCMOS DDR4 DIMM1 DQ58 data
DDR4_DIMM1_DQ59 DD12 1.2 V HS LVCMOS DDR4 DIMM1 DQ59 data
DDR4_DIMM1_DQ60 DC9 1.2 V HS LVCMOS DDR4 DIMM1 DQ60 data
DDR4_DIMM1_DQ61 DA9 1.2 V HS LVCMOS DDR4 DIMM1 DQ61 data
DDR4_DIMM1_DQ62 CY8 1.2 V HS LVCMOS DDR4 DIMM1 DQ62 data
DDR4_DIMM1_DQ63 DD8 1.2 V HS LVCMOS DDR4 DIMM1 DQ63 data
DDR4_DIMM1_DQS_P7 DD10 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 7
DDR4_DIMM1_DQS_N7 DC11 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 7
DDR4_DIMM1_DBI_N7 CY10 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 7
DDR4_DIMM1_TDQS_N16 DA11 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe for byte lane 7
DDR4_DIMM1_DQ64 CW23 1.2 V HS LVCMOS DDR4 DIMM1 DQ64 data
DDR4_DIMM1_DQ65 CV22 1.2 V HS LVCMOS DDR4 DIMM1 DQ65 data
DDR4_DIMM1_DQ66 CT22 1.2 V HS LVCMOS DDR4 DIMM1 DQ66 data
DDR4_DIMM1_DQ67 CR23 1.2 V HS LVCMOS DDR4 DIMM1 DQ67 data
DDR4_DIMM1_DQ68 CR19 1.2 V HS LVCMOS DDR4 DIMM1 DQ68 data
DDR4_DIMM1_DQ69 CV18 1.2 V HS LVCMOS DDR4 DIMM1 DQ69 data
DDR4_DIMM1_DQ70 CW19 1.2 V HS LVCMOS DDR4 DIMM1 DQ70 data
DDR4_DIMM1_DQ71 CT18 1.2 V HS LVCMOS DDR4 DIMM1 DQ71 data
DDR4_DIMM1_DQS_P8 CV20 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Positive for byte lane 8
DDR4_DIMM1_DQS_N8 CW21 1.2 V HS LVCMOS DDR4 DIMM1 Data Strobe
Negative for byte lane 8
DDR4_DIMM1_DBI_N8 CT20 1.2 V HS LVCMOS DDR4 DIMM1 Data Bus Inversion for byte lane 8
DDR4_DIMM1_TDQS_N17 CR21 1.2 V HS LVCMOS DDR4 DIMM1 Termination Data Strobe for byte lane 8
DDR4_DIMM1_C1 CN29 1.2 V HS LVCMOS DDR4 DIMM1 Stacked Device Chip ID 1
DDR4_DIMM1_C0 CP28 1.2 V HS LVCMOS DDR4 DIMM1 Stacked Device Chip ID 0
DDR4_DIMM1_BG0 CR25 1.2 V HS LVCMOS DDR4 DIMM1 Bank Group 0
DDR4_DIMM1_BA1 CT24 1.2 V HS LVCMOS DDR4 DIMM1 Bank Address 1
DDR4_DIMM1_BA0 CW25 1.2 V HS LVCMOS DDR4 DIMM1 Bank Address 0
DDR4_DIMM1_A17 CV24 1.2 V HS LVCMOS DDR4 DIMM1 Address 17
DDR4_DIMM1_A16 CR27 1.2 V HS LVCMOS DDR4 DIMM1 Address 16
DDR4_DIMM1_A15 CT26 1.2 V HS LVCMOS DDR4 DIMM1 Address 15
DDR4_DIMM1_A14 CW27 1.2 V HS LVCMOS DDR4 DIMM1 Address 14
DDR4_DIMM1_A13 CV26 1.2 V HS LVCMOS DDR4 DIMM1 Address 13
DDR4_DIMM1_A12 CR29 1.2 V HS LVCMOS DDR4 DIMM1 Address 12
DDR4_DIMM1_A11 CR31 1.2 V HS LVCMOS DDR4 DIMM1 Address 11
DDR4_DIMM1_A10 CT30 1.2 V HS LVCMOS DDR4 DIMM1 Address 10
DDR4_DIMM1_A9 CW31 1.2 V HS LVCMOS DDR4 DIMM1 Address 9
DDR4_DIMM1_A8 CV30 1.2 V HS LVCMOS DDR4 DIMM1 Address 8
DDR4_DIMM1_A7 CR33 1.2 V HS LVCMOS DDR4 DIMM1 Address 7
DDR4_DIMM1_A6 CT32 1.2 V HS LVCMOS DDR4 DIMM1 Address 6
DDR4_DIMM1_A5 CW33 1.2 V HS LVCMOS DDR4 DIMM1 Address 5
DDR4_DIMM1_A4 CV32 1.2 V HS LVCMOS DDR4 DIMM1 Address 4
DDR4_DIMM1_A3 CR35 1.2 V HS LVCMOS DDR4 DIMM1 Address 3
DDR4_DIMM1_A2 CT34 1.2 V HS LVCMOS DDR4 DIMM1 Address 2
DDR4_DIMM1_A1 CW35 1.2 V HS LVCMOS DDR4 DIMM1 Address 1
DDR4_DIMM1_A0 CV34 1.2 V HS LVCMOS DDR4 DIMM1 Address 0
DDR4_DIMM1_PAR CL31 1.2 V HS LVCMOS DDR4 DIMM1 Parity
DDR4_DIMM1_CS_N1 CK30 1.2 V HS LVCMOS DDR4 DIMM1 Chip Select 1
DDR4_DIMM1_CK_N0 CN31 1.2 V HS LVCMOS DDR4 DIMM1 Clock 0,
Positive
DDR4_DIMM1_CK_P0 CP30 1.2 V HS LVCMOS DDR4 DIMM1 Clock 0,
Negative
DDR4_DIMM1_CKE1 CL33 1.2 V HS LVCMOS DDR4 DIMM1 Clock Enable 1
DDR4_DIMM1_CKE0 CK32 1.2 V HS LVCMOS DDR4 DIMM1 Clock Enable 0
DDR4_DIMM1_ODT1 CN33 1.2 V HS LVCMOS DDR4 DIMM1 On Die Termination 1
DDR4_DIMM1_ODT0 CP32 1.2 V HS LVCMOS DDR4 DIMM1 On Die Termination 0
DDR4_DIMM1_ACT_N CL35 1.2 V HS LVCMOS DDR4 DIMM1 Activate Command
DDR4_DIMM1_CS_N0 CK34 1.2 V HS LVCMOS DDR4 DIMM1 Chip Select 0
DDR4_DIMM1_RESET_N CN35 1.2 V HS LVCMOS DDR4 DIMM1 Reset
DDR4_DIMM1_BG1 CP34 1.2 V HS LVCMOS DDR4 DIMM1 Bank Group 1
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