Intel Agilex® 7 F-Series FPGA (Two F-Tiles) Development Kit User Guide

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ID 739942
Date 8/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kits Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Applying Power to the Development Board
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass- or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install the Intel® Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFP NRZ Tab 4.2.5.2. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab
5. Development Kits Hardware and Configuration x
5.1. JTAG Configuration Mode 5.2. Active Serial (AS) x4 Configuration Mode 5.3. Avalon® -ST x16 Configuration Mode
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Intel® Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. FPGA Configuration A.3. Default Switch and Jumper Settings A.4. Input and Output Components A.5. Components and Interfaces A.6. I2C A.7. Intel® MAX® 10 SPI Bus A.8. Clock Circuits A.9. HPS Daughter Card A.10. System Power A.11. Power Guidelines A.12. Power Distribution System A.13. Power Measurement A.14. Thermal Limitations and Protection
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components A.1.3. Intel® MAX® 10 CPLD System Controller
A.2. FPGA Configuration x
A.2.1. Programming the FPGA over On-Board Intel® FPGA Download Cable II A.2.2. Programming the FPGA over an External Intel® FPGA Download Cable II
A.3. Default Switch and Jumper Settings x
A.3.1. Switch Description A.3.2. Jumper Description
A.4. Input and Output Components x
A.4.1. Push Buttons A.4.2. Switches A.4.3. LEDs
A.5. Components and Interfaces x
A.5.1. PCI Express* ( PCIe* ) Interface A.5.2. QSFP-DD Interface A.5.3. QSFP Interface A.5.4. CXL Interface A.5.5. DDR4 DIMM1 Interface A.5.6. DDR4 DIMM2 Interface A.5.7. DDR4 Component Interface A.5.8. HPS I/O48 Interface
A.11. Power Guidelines x
A.11.1. In a Standard PCIe* -Compliant System A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kits Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

A.9. HPS Daughter Card

The development kit includes an Intel® HPS daughter card that mounts to a Samtec 48-pin connector (J6) and connects to the Intel Agilex® 7 HPS I/O 48 bank. The HPS daughter card provides SoC port functionality to the development kit. These ports include Ethernet, USB, UART, I2C, JTAG, and a SD memory card slot. For more information, refer to the HPS IO-48 OOBE Daughter Card.

Figure 27. HPS Daughter Card
Table 41.  HPS I/O 48 Signals
Schematic Signal Name FPGA Pin Number I/O Standard Description
HPS_GPIO0 AC15 1.8 V LVCMOS USB clock
HPS_GPIO1 AL15 1.8 V LVCMOS USB STP
HPS_GPIO2 AJ11 1.8 V LVCMOS USB DIR
HPS_GPIO3 AM16 1.8 V LVCMOS USB DATA0
HPS_GPIO4 AH12 1.8 V LVCMOS USB DATA1
HPS_GPIO5 AN15 1.8 V LVCMOS USB NXT
HPS_GPIO6 AG13 1.8 V LVCMOS USB DATA2
HPS_GPIO7 AP16 1.8 V LVCMOS USB DATA3
HPS_GPIO8 AF14 1.8 V LVCMOS USB DATA4
HPS_GPIO9 AT16 1.8 V LVCMOS USB DATA5
HPS_GPIO10 AH10 1.8 V LVCMOS USB DATA6
HPS_GPIO11 AU15 1.8 V LVCMOS USB DATA7
HPS_GPIO12 AJ7 1.8 V LVCMOS Ethernet TX clock
HPS_GPIO13 AL13 1.8 V LVCMOS Ethernet TX CTL
HPS_GPIO14 AH8 1.8 V LVCMOS Ethernet RX clock
HPS_GPIO15 AM14 1.8 V LVCMOS Ethernet RX CTL
HPS_GPIO16 AD14 1.8 V LVCMOS Ethernet TX Data0
HPS_GPIO17 AN13 1.8 V LVCMOS Ethernet TX Data1
HPS_GPIO18 AG11 1.8 V LVCMOS Ethernet RX Data0
HPS_GPIO19 AP14 1.8 V LVCMOS Ethernet RX Data1
HPS_GPIO20 AG9 1.8 V LVCMOS Ethernet TX Data2
HPS_GPIO21 AT14 1.8 V LVCMOS Ethernet TX Data3
HPS_GPIO22 AF12 1.8 V LVCMOS Ethernet RX Data2
HPS_GPIO23 AU13 1.8 V LVCMOS Ethernet RX Data3
HPS_GPIO24 AF10 1.8 V LVCMOS GPIO I/O 0
HPS_GPIO25 AU11 1.8 V LVCMOS GPIO I/O 1
HPS_GPIO26 AF8 1.8 V LVCMOS UART TX
HPS_GPIO27 AT12 1.8 V LVCMOS UART RX
HPS_GPIO28 AG7 1.8 V LVCMOS GPIO I/O 4
HPS_GPIO29 AP12 1.8 V LVCMOS GPIO I/O 5
HPS_GPIO30 AC13 1.8 V LVCMOS I2C SDA
HPS_GPIO31 AN11 1.8 V LVCMOS I2C SCL
HPS_GPIO32 AD12 1.8 V LVCMOS JTAG TCK
HPS_GPIO33 AM12 1.8 V LVCMOS JTAG TMS
HPS_GPIO34 AD10 1.8 V LVCMOS JTAG TDO
HPS_GPIO35 AL11 1.8 V LVCMOS JTAG TDI
HPS_GPIO36 AC11 1.8 V LVCMOS SDMMC Data0
HPS_GPIO37 AT10 1.8 V LVCMOS SDMMC CMD
HPS_GPIO38 AD8 1.8 V LVCMOS SDMMC clock
HPS_GPIO39 AP10 1.8 V LVCMOS SDMMC Data1
HPS_GPIO40 AC9 1.8 V LVCMOS SDMMC Data2
HPS_GPIO41 AM10 1.8 V LVCMOS SDMMC Data3
HPS_GPIO42 AB10 1.8 V LVCMOS Clock
HPS_GPIO43 AJ13 1.8 V LVCMOS GPIO I/O 19
HPS_GPIO44 AB14 1.8 V LVCMOS GPIO I/O 20
HPS_GPIO45 AH14 1.8 V LVCMOS GPIO I/O 21
HPS_GPIO46 AB12 1.8 V LVCMOS Ethernet MDIO
HPS_GPIO47 AJ9 1.8 V LVCMOS Ethernet MDC
Level Two Title