Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide

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ID 739942
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Quartus® Prime Software and Driver Installation
2.3. Quartus® Prime Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFP NRZ Tab 4.2.5.2. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab
5. Development Kit Hardware and Configuration x
5.1. JTAG Configuration Mode 5.2. Active Serial (AS) x4 Configuration Mode 5.3. Avalon® Streaming Interface x16 Configuration Mode
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. FPGA Configuration A.3. Default Switch and Jumper Settings A.4. Input and Output Components A.5. Components and Interfaces A.6. I2C A.7. MAX® 10 SPI Bus A.8. Clock Circuits A.9. HPS Daughter Card A.10. System Power A.11. Power Guidelines A.12. Power Distribution System A.13. Power Measurement A.14. Thermal Limitations and Protection
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components A.1.3. MAX® 10 CPLD System Controller
A.2. FPGA Configuration x
A.2.1. Programming the FPGA over On-Board Intel® FPGA Download Cable II A.2.2. Programming the FPGA over an External Intel® FPGA Download Cable II
A.3. Default Switch and Jumper Settings x
A.3.1. Switch Description A.3.2. Jumper Description
A.4. Input and Output Components x
A.4.1. Push Buttons A.4.2. Switches A.4.3. LEDs
A.5. Components and Interfaces x
A.5.1. PCI Express* ( PCIe* ) Interface A.5.2. QSFP-DD Interface A.5.3. QSFP Interface A.5.4. CXL Interface A.5.5. DDR4 DIMM1 Interface A.5.6. DDR4 DIMM2 Interface A.5.7. DDR4 Component Interface A.5.8. HPS IO48 Interface
A.11. Power Guidelines x
A.11.1. In a Standard PCIe* -Compliant System A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.1.2. Board Components

Table 7.  Featured Devices
Board Reference Type Description
U8 FPGA

Agilex™ 7 FPGA, AGFD023R24C2E1VC

  • 2,308,080 Logic Elements (LE)
  • 782,400 Adaptive Logic Elements (ALM)
  • 10,464 M20K blocks
  • 39120 MLABs
  • 1640 DSP blocks
  • 3280 multipliers
  • 2 Crypto blocks
  • 480 GPIOs
  • 240 LVDS
  • 32 x 32 Gbps transceivers
  • 24 x 58 Gbps transceivers
  • 2340 pin BGA package

Agilex™ 7 FPGA, AGFB027R24C2E2V

  • 2,692,760 Logic Elements (LE)
  • 912,800 Adaptive Logic Elements (ALM)
  • 13,272 M20K blocks
  • 45,640 MLABs
  • 8,528 DSP blocks
  • 17,056 18x19 multipliers
  • 744 GPIOs
  • 372 LVDS
  • 32 x 32 Gbps transceivers
  • 24 x 58 Gbps transceivers
  • 2340 pin BGA package
U5 CPLD MAX® 10 CPLD, 10M50DAF256I7G
Table 8.  Configuration and Setup Elements
Board Reference Type Description
J10 On-board Intel® FPGA Download Cable II Micro-USB 2.0 connector for programming and debugging the FPGA.
SW1 PCIe* control DIP switch Enables PCIe* link widths x1, x4, x8, and x16.
SW2 Intel® FPGA Download Cable II selection switch Selects between the on-board Intel® FPGA Download Cable II or external Intel® FPGA Download Cable II connected to the J3 header.

SW3

Position 1-2

 JTAG bypass DIP switch Enables and disables devices in the JTAG chain.

SW3

Position 3-4

 MSEL configuration DIP switch Sets the Agilex™ 7 MSEL configuration modes
SW4 PCIe* clock control DIP switch Provides control for PCIe* clock controls such as Spread Spectrum enable/disable, local or external PCIe* clock source, and PCIe* REFCLK power down.
SW5 Power-on slide switch Main switch for powering on the Board when used in bench-top mode. This switch is ignored when the board is used in a PCIe* system.
SW6 MAX® 10 JTAGEN switch Enables MAX® 10 to use the JTAG pins as I/Os.
S1 CPU RESETn Sends an active low signal to the FPGA and MAX® 10 which can be used as the RESET for internal designs.
S2 HPS RESETn Sends an active low signal to the MAX® 10. MAX® 10 can then send HPS_DC_RSTn to the HPS IO48 daughter card is present.
S3 1st_ PCIe* _PERSTN push-button Sends an active low signal to the dedicated PCIe* _PERSTN pin of transceiver Bank 13A.
S4 2nd_ PCIe* _PERSTN push-button Sends an active low signal to a GPIO pin in Bank 3A. This pin can be used as a secondary PERSTN signal.
S6 CXL_ PCIe* _PERSTN push-button Sends an active low signal to the CXL connector PERSTN pin.
J105 Configuration image selection Use together with J106 to select image stored in U4 for Avalon® streaming interface x16.
J106 Configuration image selection Use together with J105 to select image stored in U4 for Avalon® streaming interface x16.
Table 9.  Status Elements
Board Reference Type Description
D1 Green MAX® 10 CONF_DONE LED LED is on when the MAX® 10 is successfully configured.
D2 Blue power good LED LED is on when MAX® 10 detects that all power on the board is good.
D5 Red over temperature LED LED is on when the MAX® 10 detects an over-temperature condition on the board.
D12 Green FPGA CONF_DONE LED LED is on when the FPGA is successfully configured.
D[11:8] 4 green user LEDs FPGA connected LEDs for user designs.
D[25:24] 2 green configuration image LEDs Indicates which FPGA configuration image is loaded.
Table 10.  Clock Circuits
Board Reference Type Description
U23 ZL30733 IEEE 1588 clock device I2C programmable by MAX® 10

Default frequencies:

  • Out 0: 100 MHz
  • Out 1: 125 MHz
  • Out 2: 166.25 MHz
  • Out 3: 166.25 MHz
  • Out 4: 166.25 MHz
  • Out 5: 156.25 MHz
  • Out 6: 156.25 MHz
  • Out 7: 250 MHz
  • Out 8: 184.32 MHz
  • Out 9: 153.6 MHz
U25, U26, U27

PCIe* reference clocks

  • U25: I2C programmable by MAX® 10 local
  • U26, U27: PCIe* fan-out clock buffers

Default frequencies:

  • U25:
    • Out 0: Local 100 MHz PCIe* to U26
    • Out 1: Local 100 MHz PCIe* to U27
    • Out 2: 100 MHz CXL PCIe* root port clock to CXL connector J9
  • U26:
    • Out 0: 100 MHz PCIe* Bank 13A, CH5
    • Out 1: 100 MHz PCIe* Bank 13A, CH2
  • U27:
    • Out 0: 100 MHz PCIe* Bank 12C, CH0
    • Out 1: 100 MHz PCIe* Bank 12C, CH1
Table 11.  Transceiver Interfaces
Board Reference Type Description
J1 PCIe* x16 gold fingers PCIe* TX/RX x16 interface from FPGA Bank 13A.
J7, B1 QSFPDD-56 pluggable optics interface 8 TX/RX channels from FPGA Bank 12C, Quad2 and Quad3.
J8, B2 QSFP-56 pluggable optics interface 4 TX/RX channels from FPGA Bank 12C, Quad1.
J9 PCIe* x4 over CXL connector PCIe* TX/RX x4 interface from FPGA Bank 12C, Quad0.
Table 12.  Memory Devices
Board Reference Type Description
J4 DDR4 DIMM1 connector DDR4 x72 DIMM module installed by default.
J5 DDR4 DIMM2 connector No DDR4 DIMM module installed by default.
Note: DIMM2 (J5) is not available in the Agilex™ 7 AGFD023R24C2E1VC development kit.
U15–U19 DDR4 components DDR4 x40 interface for HPS.
U3, U4 2 x 2 Gbit QSPI flash FPGA Avalon® streaming interface x16 configuration flash memory.
U9 2 Gbit QSPI flash FPGA AS x4 configuration flash memory.
U45 64 Mbit serial nor flash MAX® 10 Nios® II flash.
U44 128 Kbit I2C EEPROM MAC address EEPROM.
U46 128 Kbit I2C EEPROM Security certificate EEPROM.
Table 13.  Communication Ports
Board Reference Type Description
J3 10-pin JTAG header For connecting an external Intel® FPGA Download Cable II dongle.
J10 Micro-USB connector For connecting to the on-board Intel® FPGA Download Cable II.
Table 14.  Miscellaneous Ports
Board Reference Type Description
J2 FAN header 4-pin FAN header
J13 LTC3888 (U61) programming header Programming header for LTC3888 VCC Core, VCC_HSSI voltage regulator
J107 LTC7132 (U93, U96) programming header Programming header for U93 (LTC7132 VCCERT_FGT_GXF, VCCR_CORE) and U96 (LTC7132 VCC_PT, VCCIO_1V2)
Table 15.  Power Supplies
Board Reference Type Description
J11 12V_AUX power connector 8-pin 12V_AUX input power connector
U50 MAX16545B device Input power conditioner for 12V_ PCIe*
U54 MAX16545B device Input power conditioner for 12V_AUX
U94 Analog Devices LTM4625* 5 V DC-DC voltage regulator
U56 Intersil ISL80101* 2.5 V LDO voltage regulator
U57 Intersil ISL80101 1.8 V LDO voltage regulator
U58 Intersil ISL80101 1.2 V LDO voltage regulator
U95 Analog Devices LTM4620A* 3.3 V DC-DC voltage regulator
U60, Q18 Analog Devices LTC1981*, pass FET 3.3V_SYS voltage
U61, U62–U65 Analog Devices LTC3888* multiphase controller and FET power stage 0.8 V VCC core VID voltage regulator
U61, U66 Analog Devices LTC3888 multiphase controller and FET power stage 0.8 V VCC_HSSI_GXF voltage regulator
U80 Intersil ISL80101 0.9 V VCCH_SDM LDO voltage regulator
U93 Analog Devices LTC7132* dual-output regulator 1.0 V VCCERT_FGT_GXF voltage regulator
1.2 V VCCR_CORE voltage regulator
U96 Analog Devices LTC7132 dual-output regulator 1.8 V VCCPT voltage regulator
1.2 V VCCIO_1V2 voltage regulator
U70 Intersil ISL80101 1.0 V VCCFUSEWR_GXF LDO voltage regulator
D28 LT1389 VREF generation 1.25 V VREF for VCCBAT
U74 Intersil ISL80101 1.8 V VCCIO_SDM_HPS LDO voltage regulator
U75 Intersil ISL80101 2.5 V DDR4 DIMM LDO voltage regulator
U76 Intersil ISL80101 2.5 V DDR4 COMP LDO voltage regulator
U77 Texas Instruments TPS51200* 0.6 V DDR4 DIMM VTT/VREF generation
U78 Texas Instruments TPS51200 0.6 V DDR4 COMP VTT/VREF generation
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