Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide

Download PDF
ID 739942
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Quartus® Prime Software and Driver Installation
2.3. Quartus® Prime Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFP NRZ Tab 4.2.5.2. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab
5. Development Kit Hardware and Configuration x
5.1. JTAG Configuration Mode 5.2. Active Serial (AS) x4 Configuration Mode 5.3. Avalon® Streaming Interface x16 Configuration Mode
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. FPGA Configuration A.3. Default Switch and Jumper Settings A.4. Input and Output Components A.5. Components and Interfaces A.6. I2C A.7. MAX® 10 SPI Bus A.8. Clock Circuits A.9. HPS Daughter Card A.10. System Power A.11. Power Guidelines A.12. Power Distribution System A.13. Power Measurement A.14. Thermal Limitations and Protection
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components A.1.3. MAX® 10 CPLD System Controller
A.2. FPGA Configuration x
A.2.1. Programming the FPGA over On-Board Intel® FPGA Download Cable II A.2.2. Programming the FPGA over an External Intel® FPGA Download Cable II
A.3. Default Switch and Jumper Settings x
A.3.1. Switch Description A.3.2. Jumper Description
A.4. Input and Output Components x
A.4.1. Push Buttons A.4.2. Switches A.4.3. LEDs
A.5. Components and Interfaces x
A.5.1. PCI Express* ( PCIe* ) Interface A.5.2. QSFP-DD Interface A.5.3. QSFP Interface A.5.4. CXL Interface A.5.5. DDR4 DIMM1 Interface A.5.6. DDR4 DIMM2 Interface A.5.7. DDR4 Component Interface A.5.8. HPS IO48 Interface
A.11. Power Guidelines x
A.11.1. In a Standard PCIe* -Compliant System A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.5.7. DDR4 Component Interface

The Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit board provides a DDR4 x40 Interface comprised of five DDR4 x8 components for HPS access. This gives 32-bits data plus 8-bits ECC, which are connected to IO96 of bank 3D.

Table 34.  DDR4 Component Pin Assignments
Schematic Signal Name FPGA Pin Number I/O Standard Description
DDR4_COMP_DQ0 F12 1.2 V HS LVCMOS DDR4 component DQ0 data
DDR4_COMP_DQ1 F8 1.2 V HS LVCMOS DDR4 component DQ1 data
DDR4_COMP_DQ2 G11 1.2 V HS LVCMOS DDR4 component DQ2 data
DDR4_COMP_DQ3 K8 1.2 V HS LVCMOS DDR4 component DQ3 data
DDR4_COMP_DQ4 J11 1.2 V HS LVCMOS DDR4 component DQ4 data
DDR4_COMP_DQ5 G7 1.2 V HS LVCMOS DDR4 component DQ5 data
DDR4_COMP_DQ6 K12 1.2 V HS LVCMOS DDR4 component DQ6 data
DDR4_COMP_DQ7 J7 1.2 V HS LVCMOS DDR4 component DQ7 data
DDR4_COMP_DQS_P0 G9 1.2 V HS LVCMOS DDR4 component DQS 0 strobe positive
DDR4_COMP_DQS_N0 F10 1.2 V HS LVCMOS DDR4 component DQS 0 strobe negative
DDR4_COMP_DBI_N0 J9 1.2 V HS LVCMOS DDR4 component Data Bus Inversion for byte lane 0
DDR4_COMP_DQ8 M6 1.2 V HS LVCMOS DDR4 component DQ8 data
DDR4_COMP_DQ9 P2 1.2 V HS LVCMOS DDR4 component DQ9 data
DDR4_COMP_DQ10 L5 1.2 V HS LVCMOS DDR4 component DQ10 data
DDR4_COMP_DQ11 R1 1.2 V HS LVCMOS DDR4 component DQ11 data
DDR4_COMP_DQ12 P6 1.2 V HS LVCMOS DDR4 component DQ12 data
DDR4_COMP_DQ13 R5 1.2 V HS LVCMOS DDR4 component DQ13 data
DDR4_COMP_DQ14 M2 1.2 V HS LVCMOS DDR4 component DQ14 data
DDR4_COMP_DQ15 L1 1.2 V HS LVCMOS DDR4 component DQ15 data
DDR4_COMP_DQS_P1 L3 1.2 V HS LVCMOS DDR4 component DQS 1 strobe positive
DDR4_COMP_DQS_N1 M4 1.2 V HS LVCMOS DDR4 component DQS 1 strobe negative
DDR4_COMP_DBI_N1 R3 1.2 V HS LVCMOS DDR4 component Data Bus Inversion for byte lane 1
DDR4_COMP_DQ16 A9 1.2 V HS LVCMOS DDR4 component DQ16 data
DDR4_COMP_DQ17 B6 1.2 V HS LVCMOS DDR4 component DQ17 data
DDR4_COMP_DQ18 E9 1.2 V HS LVCMOS DDR4 component DQ18 data
DDR4_COMP_DQ19 D6 1.2 V HS LVCMOS DDR4 component DQ19 data
DDR4_COMP_DQ20 D10 1.2 V HS LVCMOS DDR4 component DQ20 data
DDR4_COMP_DQ21 C5 1.2 V HS LVCMOS DDR4 component DQ21 data
DDR4_COMP_DQ22 B10 1.2 V HS LVCMOS DDR4 component DQ22 data
DDR4_COMP_DQ23 E5 1.2 V HS LVCMOS DDR4 component DQ23 data
DDR4_COMP_DQS_P2 A7 1.2 V HS LVCMOS DDR4 component DQS 2 strobe positive
DDR4_COMP_DQS_N2 B8 1.2 V HS LVCMOS DDR4 component DQS 2 strobe negative
DDR4_COMP_DBI_N2 E7 1.2 V HS LVCMOS DDR4 component Data Bus Inversion for byte lane 2
DDR4_COMP_DQ24 F6 1.2 V HS LVCMOS DDR4 component DQ24 data
DDR4_COMP_DQ25 J1 1.2 V HS LVCMOS DDR4 component DQ25 data
DR4_COMP_DQ26 F2 1.2 V HS LVCMOS DDR4 component DQ26 data
DDR4_COMP_DQ27 K2 1.2 V HS LVCMOS DDR4 component DQ27 data
DDR4_COMP_DQ28 K6 1.2 V HS LVCMOS DDR4 component DQ28 data
DDR4_COMP_DQ29 J5 1.2 V HS LVCMOS DDR4 component DQ29 data
DDR4_COMP_DQ30 G5 1.2 V HS LVCMOS DDR4 component DQ30 data
DDR4_COMP_DQ31 G1 1.2 V HS LVCMOS DDR4 component DQ31 data
DDR4_COMP_DQS_P3 G3 1.2 V HS LVCMOS DDR4 component DQS 3 strobe positive
DDR4_COMP_DQS_N3 F4 1.2 V HS LVCMOS DDR4 component DQS 3 strobe negative
DDR4_COMP_DBI_N3 J3 1.2 V HS LVCMOS DDR4 component Data Bus Inversion for byte lane 3
DDR4_COMP_DQ32 AA7 1.2 V HS LVCMOS DDR4 component DQ32 data
DDR4_COMP_DQ33 AD2 1.2 V HS LVCMOS DDR4 component DQ33 data
DDR4_COMP_DQ34 AB2 1.2 V HS LVCMOS DDR4 component DQ34 data
DDR4_COMP_DQ35 AB8 1.2 V HS LVCMOS DDR4 component DQ35 data
DDR4_COMP_DQ36 AA1 1.2 V HS LVCMOS DDR4 component DQ36 data
DDR4_COMP_DQ37 AE7 1.2 V HS LVCMOS DDR4 component DQ37 data
DDR4_COMP_DQ38 AE1 1.2 V HS LVCMOS DDR4 component DQ38 data
DDR4_COMP_DQ39 AD6 1.2 V HS LVCMOS DDR4 component DQ39 data
DDR4_COMP_DQS_P4 AA5 1.2 V HS LVCMOS DDR4 component DQS 4 strobe positive
DDR4_COMP_DQS_N4 AB6 1.2 V HS LVCMOS DDR4 component DQS 4 strobe negative
DDR4_COMP_DBI_N4 AA3 1.2 V HS LVCMOS DDR4 component Data Bus Inversion for byte lane 4
DDR4_COMP_BG0 Y2 1.2 V HS LVCMOS DDR4 Component Bank
Group 0
DDR4_COMP_BA1 W1 1.2 V HS LVCMOS DDR4 Component Bank Address 1
DDR4_COMP_BA0 T2 1.2 V HS LVCMOS DDR4 Component Bank Address 0
DDR4_COMP_ALERT_N U1 1.2 V HS LVCMOS DDR4 Component Alert
DDR4_COMP_A16 Y4 1.2 V HS LVCMOS DDR4 Component Address 16
DDR4_COMP_A15 W3 1.2 V HS LVCMOS DDR4 Component Address 15
DDR4_COMP_A14 T4 1.2 V HS LVCMOS DDR4 Component Address 14
DDR4_COMP_A13 U3 1.2 V HS LVCMOS DDR4 Component Address 13
DDR4_COMP_A12 Y6 1.2 V HS LVCMOS DDR4 Component Address 12
DDR4_COMP_A11 Y8 1.2 V HS LVCMOS DDR4 Component Address 11
DDR4_COMP_A10 W7 1.2 V HS LVCMOS DDR4 Component Address 10
DDR4_COMP_A9 T8 1.2 V HS LVCMOS DDR4 Component Address 9
DDR4_COMP_A8 U7 1.2 V HS LVCMOS DDR4 Component Address 8
DDR4_COMP_A7 Y10 1.2 V HS LVCMOS DDR4 Component Address 7
DDR4_COMP_A6 W9 1.2 V HS LVCMOS DDR4 Component Address 6
DDR4_COMP_A5 T10 1.2 V HS LVCMOS DDR4 Component Address 5
DDR4_COMP_A4 U9 1.2 V HS LVCMOS DDR4 Component Address 4
DDR4_COMP_A3 Y12 1.2 V HS LVCMOS DDR4 Component Address 3
DDR4_COMP_A2 W11 1.2 V HS LVCMOS DDR4 Component Address 2
DDR4_COMP_A1 T12 1.2 V HS LVCMOS DDR4 Component Address 1
DDR4_COMP_A0 U11 1.2 V HS LVCMOS DDR4 Component Address 0
DDR4_COMP_PAR P8 1.2 V HS LVCMOS DDR4 Component Parity
DDR4_COMP_CK_N M8 1.2 V HS LVCMOS DDR4 DIMM2 Clock Negative
DDR4_COMP_CK_P L7 1.2 V HS LVCMOS DDR4 DIMM2 Clock Positive
DDR4_COMP_CKE R9 1.2 V HS LVCMOS DDR4 Component Clock Enable
DDR4_COMP_ODT L9 1.2 V HS LVCMOS DDR4 Component On Die Termination
DDR4_COMP_ACT_N P12 1.2 V HS LVCMOS DDR4 Component Activate
DDR4_COMP_CS_N R11 1.2 V HS LVCMOS DDR4 Component Chip Select
DDR4_COMP_RESET_N M12 1.2 V HS LVCMOS DDR4 Component Reset
DDR4_COMP_BG1 L11 1.2 V HS LVCMOS DDR4 Component Bank Group 1
Level Two Title