Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide

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ID 739942
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Quartus® Prime Software and Driver Installation
2.3. Quartus® Prime Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFP NRZ Tab 4.2.5.2. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab
5. Development Kit Hardware and Configuration x
5.1. JTAG Configuration Mode 5.2. Active Serial (AS) x4 Configuration Mode 5.3. Avalon® Streaming Interface x16 Configuration Mode
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. FPGA Configuration A.3. Default Switch and Jumper Settings A.4. Input and Output Components A.5. Components and Interfaces A.6. I2C A.7. MAX® 10 SPI Bus A.8. Clock Circuits A.9. HPS Daughter Card A.10. System Power A.11. Power Guidelines A.12. Power Distribution System A.13. Power Measurement A.14. Thermal Limitations and Protection
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components A.1.3. MAX® 10 CPLD System Controller
A.2. FPGA Configuration x
A.2.1. Programming the FPGA over On-Board Intel® FPGA Download Cable II A.2.2. Programming the FPGA over an External Intel® FPGA Download Cable II
A.3. Default Switch and Jumper Settings x
A.3.1. Switch Description A.3.2. Jumper Description
A.4. Input and Output Components x
A.4.1. Push Buttons A.4.2. Switches A.4.3. LEDs
A.5. Components and Interfaces x
A.5.1. PCI Express* ( PCIe* ) Interface A.5.2. QSFP-DD Interface A.5.3. QSFP Interface A.5.4. CXL Interface A.5.5. DDR4 DIMM1 Interface A.5.6. DDR4 DIMM2 Interface A.5.7. DDR4 Component Interface A.5.8. HPS IO48 Interface
A.11. Power Guidelines x
A.11.1. In a Standard PCIe* -Compliant System A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.5.1. PCI Express* ( PCIe* ) Interface

The Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit board is designed to fit entirely into a PC motherboard with a x16 PCI Express* slot that can accommodate a full height, 2-slot, ¾ length form factor add-in card. This interface uses the Agilex™ 7 FPGA's PCI Express* hard IP block, saving logic resources for the user logic application. The PCI Express* edge connector has a presence detect feature to allow the motherboard to determine if a card is installed.

The PCI Express* interface supports auto-negotiating channel width from x1 to x4 to x8 to x16 by using PCIe* Intel FPGA IP. You can also configure this board to a x1, x4, x8, or x16 interface through a DIP switch that connects the PRSTn pins for each bus width.

The PCI Express* edge connector has a connection speed of 2.5 Gbps/lane for a maximum of 40 Gbps full-duplex ( PCIe* 1.0), 5.0 Gbps/lane for maximum of 80 Gbps full-duplex ( PCIe* 2.0), or 8.0 Gbps/lane for a maximum of 128 Gbps full-duplex ( PCIe* 3.0), and 16.0 Gbps/lane for a maximum of 256 Gbps full-duplex ( PCIe* 4.0).

The power for the board can be sourced entirely from the PC host when installed into a PC motherboard with the PC’s 2x4 ATX auxiliary power connected to the 12V ATX inputs (J11) of the Agilex™ 7 FPGA (two F-Tiles) development board. Although the board can also be powered by an externally supplied power supply for use on a lab bench, Altera recommends that you do not power up from both supplies at the same time. Ideal diode power sharing devices have been designed into this board to prevent damages or backcurrent from one supply to the other.

The REFCLK_PCIE_EP_EDGE_P/N signal is a 100 MHz differential input that is driven from the PC motherboard onto this board through the edge connector. This signal connects directly to a Agilex™ 7 FPGA REFCLK input pin pair using DC coupling. This clock is terminated on the motherboard. Therefore, no on-board termination is required. This clock can have spread-spectrum properties that change its period between 9.847 ps to 10.203 ps. The I/O standard is high-speed current steering logic (HCSL).

Table 28.   PCI Express* ( PCIe* ) Pin Assignments
Edge Finger Pin Number Schematic Signal Name FPGA Pin Number I/O Standard Description
A11 PCIE_3V3_EP_PERSTN MAX10 (U5) 3V LVCMOS Reset
A14 REFCLK_PCIE_EP_EDGE_N Clock Buffer (U26) LVDS Motherboard reference
clock
A13 REFCLK_PCIE_EP_EDGE_P Clock Buffer (U26) LVDS Motherboard reference
clock
B5 PCIE_3V3_EP_SMBCLK FRUID EEPROM (U2) 1.8V SMB clock
B6 PCIE_3V3_EP_SMBDAT FRUID EEPROM (U2) 1.8V SMB data
A1 PCIE_EP_PRSNT_N — — Link with DIP switch
(SW1)
B17 PCIE_EP_PRSNT_Nx1 — — Link with DIP switch
(SW1)
B31 PCIE_EP_PRSNT_Nx4 — — Link with DIP switch
(SW1)
B48 PCIE_EP_PRSNT_Nx8 — — Link with DIP switch
(SW1)
B81 PCIE_EP_PRSNT_Nx16 — — Link with DIP switch
(SW1)
B15 PCIE_EP_TX_N0 AG5 1.4 V PCML Receive bus
B20 PCIE_EP_TX_N1 AH2 1.4 V PCML Receive bus
B24 PCIE_EP_TX_N2 AM2 1.4 V PCML Receive bus
B28 PCIE_EP_TX_N3 AT2 1.4 V PCML Receive bus
B34 PCIE_EP_TX_N4 AY2 1.4 V PCML Receive bus
B38 PCIE_EP_TX_N5 BD2 1.4 V PCML Receive bus
B42 PCIE_EP_TX_N6 BH2 1.4 V PCML Receive bus
B46 PCIE_EP_TX_N7 BM2 1.4 V PCML Receive bus
B51 PCIE_EP_TX_N8 BT2 1.4 V PCML Receive bus
B55 PCIE_EP_TX_N9 BY2 1.4 V PCML Receive bus
B59 PCIE_EP_TX_N10 CD2 1.4 V PCML Receive bus
B63 PCIE_EP_TX_N11 CH2 1.4 V PCML Receive bus
B67 PCIE_EP_TX_N12 CM2 1.4 V PCML Receive bus
B71 PCIE_EP_TX_N13 CR5 1.4 V PCML Receive bus
B75 PCIE_EP_TX_N14 CT2 1.4 V PCML Receive bus
B79 PCIE_EP_TX_N5 CW5 1.4 V PCML Receive bus
B14 PCIE_EP_TX_P0 AF4 1.4 V PCML Receive bus
B19 PCIE_EP_TX_P1 AJ1 1.4 V PCML Receive bus
B23 PCIE_EP_TX_P2 AN1 1.4 V PCML Receive bus
B27 PCIE_EP_TX_P3 AU1 1.4 V PCML Receive bus
B33 PCIE_EP_TX_P4 BA1 1.4 V PCML Receive bus
B37 PCIE_EP_TX_P5 BE1 1.4 V PCML Receive bus
B41 PCIE_EP_TX_P6 BJ1 1.4 V PCML Receive bus
B45 PCIE_EP_TX_P7 BN1 1.4 V PCML Receive bus
B50 PCIE_EP_TX_P8 BU1 1.4 V PCML Receive bus
B54 PCIE_EP_TX_P9 CA1 1.4 V PCML Receive bus
B58 PCIE_EP_TX_P10 CE1 1.4 V PCML Receive bus
B62 PCIE_EP_TX_P11 CJ1 1.4 V PCML Receive bus
B66 PCIE_EP_TX_P12 CN1 1.4 V PCML Receive bus
B70 PCIE_EP_TX_P13 CP4 1.4 V PCML Receive bus
B74 PCIE_EP_TX_P14 CU1 1.4 V PCML Receive bus
B78 PCIE_EP_TX_P15 CV4 1.4 V PCML Receive bus
A17 PCIE_EP_RX_N0 AL5 1.4 V PCML Transmit bus
A22 PCIE_EP_RX_N1 AM8 1.4 V PCML Transmit bus
A26 PCIE_EP_RX_N2 AR5 1.4 V PCML Transmit bus
A30 PCIE_EP_RX_N3 AT8 1.4 V PCML Transmit bus
A36 PCIE_EP_RX_N4 AW5 1.4 V PCML Transmit bus
A40 PCIE_EP_RX_N5 AY8 1.4 V PCML Transmit bus
A44 PCIE_EP_RX_N6 BC5 1.4 V PCML Transmit bus
A48 PCIE_EP_RX_N7 BG5 1.4 V PCML Transmit bus
A53 PCIE_EP_RX_N8 BL5 1.4 V PCML Transmit bus
A57 PCIE_EP_RX_N9 BR5 1.4 V PCML Transmit bus
A61 PCIE_EP_RX_N10 BW5 1.4 V PCML Transmit bus
A65 PCIE_EP_RX_N11 CC5 1.4 V PCML Transmit bus
A69 PCIE_EP_RX_N12 CG5 1.4 V PCML Transmit bus
A73 PCIE_EP_RX_N13 CL5 1.4 V PCML Transmit bus
A77 PCIE_EP_RX_N14 CM8 1.4 V PCML Transmit bus
A81 PCIE_EP_RX_N15 CT8 1.4 V PCML Transmit bus
A16 PCIE_EP_RX_P0 AK4 1.4 V PCML Transmit bus
A21 PCIE_EP_RX_P1 AN7 1.4 V PCML Transmit bus
A25 PCIE_EP_RX_P2 AP4 1.4 V PCML Transmit bus
A29 PCIE_EP_RX_P3 AU7 1.4 V PCML Transmit bus
A35 PCIE_EP_RX_P4 AV4 1.4 V PCML Transmit bus
A39 PCIE_EP_RX_P5 BA7 1.4 V PCML Transmit bus
A43 PCIE_EP_RX_P6 BB4 1.4 V PCML Transmit bus
A47 PCIE_EP_RX_P7 BF4 1.4 V PCML Transmit bus
A52 PCIE_EP_RX_P8 BK4 1.4 V PCML Transmit bus
A56 PCIE_EP_RX_P9 BP4 1.4 V PCML Transmit bus
A60 PCIE_EP_RX_P10 BV4 1.4 V PCML Transmit bus
A64 PCIE_EP_RX_p11 CB4 1.4 V PCML Transmit bus
A68 PCIE_EP_RX_P12 CF4 1.4 V PCML Transmit bus
A72 PCIE_EP_RX_P13 CK4 1.4 V PCML Transmit bus
A76 PCIE_EP_RX_P14 CN7 1.4 V PCML Transmit bus
A80 PCIE_EP_RX_P15 CU7 1.4 V PCML Transmit bus
B11 PCIE_3V3_EP_WAKE — 3.3V Wake Signal
B12 PCIE_3V3_EP_CLKREQn — 3.3V Clock Request
Level Two Title