Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide

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ID 739942
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Quartus® Prime Software and Driver Installation
2.3. Quartus® Prime Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Board
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFP NRZ Tab 4.2.5.2. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab
5. Development Kit Hardware and Configuration x
5.1. JTAG Configuration Mode 5.2. Active Serial (AS) x4 Configuration Mode 5.3. Avalon® Streaming Interface x16 Configuration Mode
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. FPGA Configuration A.3. Default Switch and Jumper Settings A.4. Input and Output Components A.5. Components and Interfaces A.6. I2C A.7. MAX® 10 SPI Bus A.8. Clock Circuits A.9. HPS Daughter Card A.10. System Power A.11. Power Guidelines A.12. Power Distribution System A.13. Power Measurement A.14. Thermal Limitations and Protection
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components A.1.3. MAX® 10 CPLD System Controller
A.2. FPGA Configuration x
A.2.1. Programming the FPGA over On-Board Intel® FPGA Download Cable II A.2.2. Programming the FPGA over an External Intel® FPGA Download Cable II
A.3. Default Switch and Jumper Settings x
A.3.1. Switch Description A.3.2. Jumper Description
A.4. Input and Output Components x
A.4.1. Push Buttons A.4.2. Switches A.4.3. LEDs
A.5. Components and Interfaces x
A.5.1. PCI Express* ( PCIe* ) Interface A.5.2. QSFP-DD Interface A.5.3. QSFP Interface A.5.4. CXL Interface A.5.5. DDR4 DIMM1 Interface A.5.6. DDR4 DIMM2 Interface A.5.7. DDR4 Component Interface A.5.8. HPS IO48 Interface
A.11. Power Guidelines x
A.11.1. In a Standard PCIe* -Compliant System A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.5.2. QSFP-DD Interface

The Agilex™ 7 FPGA F-Series (2 × F-Tiles) Development Kit board includes a connector and cages system for mounting a Double Density Quad Small Form-Factor Pluggable (QSFP-DD) module. The interface connects to eight 56 Gbps PAM4 capable F-Tile lanes of the Agilex™ 7 FPGA, supporting QSFP-DD modules, with capability of 400 Gbps aggregate bandwidth with power classifications up to 10 W.

Table 29.  QSFP-DD Pin Assignments
Schematic Signal Name FPGA Pin Number I/O Standard Description
QSFPDD_TX0_P AV52 True Differential Signaling QSFPDD Transmit Channel 0 Positive
QSFPDD_TX0_N AU51 True Differential Signaling QSFPDD Transmit Channel 0 negative
QSFPDD_TX1_P R49 True Differential Signaling QSFPDD Transmit Channel 1 Positive
QSFPDD_TX1_N T48 True Differential Signaling QSFPDD Transmit Channel 1 negative
QSFPDD_TX2_P AN51 True Differential Signaling QSFPDD Transmit Channel 2 Positive
QSFPDD_TX2_N AP52 True Differential Signaling QSFPDD Transmit Channel 2 negative
QSFPDD_TX3_P U51 True Differential Signaling QSFPDD Transmit Channel 3 Positive
QSFPDD_TX3_N V52 True Differential Signaling QSFPDD Transmit Channel 3 negative
QSFPDD_TX4_P AF52 True Differential Signaling QSFPDD Transmit Channel 4 Positive
QSFPDD_TX4_N AE51 True Differential Signaling QSFPDD Transmit Channel 4 negative
QSFPDD_TX5_P Y48 True Differential Signaling QSFPDD Transmit Channel 5 Positive
QSFPDD_TX5_N W49 True Differential Signaling QSFPDD Transmit Channel 5 negative
QSFPDD_TX6_P AJ51 True Differential Signaling QSFPDD Transmit Channel 6 Positive
QSFPDD_TX6_N AK52 True Differential Signaling QSFPDD Transmit Channel 6 negative
QSFPDD_TX7_P AA51 True Differential Signaling QSFPDD Transmit Channel 7 Positive
QSFPDD_TX7_N AB52 True Differential Signaling QSFPDD Transmit Channel 7 negative
QSFPDD_RX0_P AR55 True Differential Signaling QSFPDD Receive Channel 0 Positive
QSFPDD_RX0_N AT54 True Differential Signaling QSFPDD Receive Channel 0 negative
QSFPDD_RX1_P K52 True Differential Signaling QSFPDD Receive Channel 1 Positive
QSFPDD_RX1_N J51 True Differential Signaling QSFPDD Receive Channel 1 negative
QSFPDD_RX2_P AL55 True Differential Signaling QSFPDD Receive Channel 2 Positive
QSFPDD_RX2_N AM54 True Differential Signaling QSFPDD Receive Channel 2 negative
QSFPDD_RX3_P P52 True Differential Signaling QSFPDD Receive Channel 3 Positive
QSFPDD_RX3_N N51 True Differential Signaling QSFPDD Receive Channel 3 negative
QSFPDD_RX4_P AC55 True Differential Signaling QSFPDD Receive Channel 4 Positive
QSFPDD_RX4_N AD54 True Differential Signaling QSFPDD Receive Channel 4 negative
QSFPDD_RX5_P R55 True Differential Signaling QSFPDD Receive Channel 5 Positive
QSFPDD_RX5_N T54 True Differential Signaling QSFPDD Receive Channel 5 negative
QSFPDD_RX6_P AG55 True Differential Signaling QSFPDD Receive Channel 6 Positive
QSFPDD_RX6_N AH54 True Differential Signaling QSFPDD Receive Channel 6 negative
QSFPDD_RX7_P W55 True Differential Signaling QSFPDD Receive Channel 7 Positive
QSFPDD_RX7_N Y54 True Differential Signaling QSFPDD Receive Channel 7 negative
QSFPDD_REFCLK_P AD48 LVPECL QSFPDD Reference Clock Positive
QSFPDD_REFCLK_N AC49 LVPECL QSFPDD Reference Clock Negative
QSFPDD_LED1 (Yellow LED) G49 1.2V HS LVCMOS QSFPDD Yellow LED
QSFPDD_LED2 (Green LED) F48 1.2V HS LVCMOS QSFPDD Green LED
Note: For more information about Altera's True Differential Signaling technology, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series.
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