F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

1.7. Testing the Hardware Design Example

The F-Tile Dyamic Recofiguatio Desig Example us the exteal loopback test by default with the loopback_mode paamete set to 0. Befoe pefomig ay hadwae test, attach the QSFP-DD loopback module accodig to the QSF piout assigmets of the espective desig example. To pefom a iteal loopback test i hadwae, modify the loopback_mode paamete to 1 i the paamete.tcl file located i <desig_example_di>/hadwae_test_desig/hwtest/sc. Afte you compile the F-Tile dyamic ecofiguatio desig example ad cofigue it o you Agilex™ 7 device, you ca use the System Cosole to pogam the IP coe ad its PHY IP coe egistes.

The hadwae desig example executes the dyamic ecofiguatio tasitio pocess based o you selectios as stated i <desig_example_di>/hadwae_test_desig/hwtest/sc/paamete.tcl file ad checks the DUT IP status. The dyamic ecofiguatio tasitio sequece is set by default. Howeve, you ca always chage it by modifyig the DR_TRANSITION aay vaiable i thepaamete.tcl file to chage the tasitio sequece.

DR_TRANSITION: Iteded dyamic ecofiguatio sequece aay. The size of this aay vaiable detemies the umbe of dyamic ecofiguatios to be pefomed.

To stat the System Cosole ad test the hadwae desig example, follow these steps:

  1. Afte the hadwae desig example is cofigued o the Agilex™ 7 device, i the Quatus® Pime Po Editio softwae, click Tools > System Debuggig Tools > System Cosole.
  2. I the Tcl Cosole pae, type cd hwtest to chage diectoy to <desig_example_di>/hadwae_test_desig/hwtest.
  3. Type souce mai_scipt.tcl to ope a coectio to the JTAG maste ad stat the test.
  4. Aalyze the esults. Successful u displays Test Passed i the System Cosole.
    Note: If iteal seial loopback (ILB) is eabled fo the cuet pofile, you eed to disable it usig the FGT attibute access method befoe pefomig dyamic ecofiguatio to the ext taget pofile. If you do ot follow this, you might obseve that the Quatus Had IP pefoms abomally afte dyamic ecofiguatio.

    The ifomatio i this sectio fo testig the desig example i hadwae applies to the followig dyamic ecofiguatio desig example:

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