F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

1.3. Directory Structure

The F-Tile Dyamic Recofiguatio desig example geeates the followig files:
Table 6.  Testbech File Desciptios fo Desig Example
File Names Desciptio
Key Testbech ad Simulatio Files fo CPRI Multiate Desigs
<desig_example_di>/example_testbech/basic_avl_tb_top.sv Top-level testbech file. The testbech istatiates the DUT wappe ad us Veilog HDL tasks to geeate ad accept packets.
<desig_example_di>/example_testbech/cpiphy_d_ed_dut_wappe.sv DUT wappe that istatiates DUT ad othe testbech compoets.
<desig_example_di>/example_testbech/ cpiphy_d_ed_hw.sv Top hadwae desig file. This file istatiates the F-Tile Dyamic Recofiguatio Suite Itel FPGA IP, F-Tile Refeece ad System PLL Clocks Itel FPGA IP, ad DUT wappe.
Key Testbech ad Simulatio Files fo Etheet Multiate Desigs
<desig_example_di>/example_testbech/basic_avl_tb_top.sv Top-level testbech file. The testbech istatiates the DUT wappe ad us Veilog HDL tasks to geeate ad accept packets.
<desig_example_di>/example_testbech/ eth_f_hw.sv DUT wappe that istatiates DUT ad othe testbech compoets.
Key Testbech ad Simulatio Files fo PMA/FEC Diect PHY Multiate Desigs
<desig_example_di>/example_testbech/top_tst.sv Top-level testbech file. The testbech istatiates the DUT wappe ad us Veilog HDL tasks to geeate ad eceive PRBS data steam.
<desig_example_di>/example_testbech/dphy_f_hw.sv DUT wappe that istatiates PMA/FEC Diect PHY Multiate DUT ad othe testbech compoets.
Key Testbech ad Simulatio Files fo Etheet to CPRI Multiate Desigs
<desig_example_di>/example_testbech/basic_avl_tb_top.sv Top-level testbech file. The testbech istatiates the DUT wappe ad us Veilog HDL tasks to geeate ad accept packets.
<desig_example_di>/example_testbech/eth_cpiphy_f_hw.sv Top wappe that istatiates Etheet ad CPRI PHY Multiate DUT ad othe testbech compoets.
Testbech Scipts fo CPRI, Etheet, PMA/FEC Diect PHY, ad Etheet to CPRI Multiate Desigs
<desig_example_di>/example_testbech/u_vsim.do The QuestaSim* scipt to u the testbech.
<desig_example_di>/example_testbech/u_vcs.sh The VCS* scipt to u the testbech.
<desig_example_di>/example_testbech/u_vcsmx.sh The VCS* MX scipt to u the testbech.
<desig_example_di>/example_testbech/ u_xcelium.sh The Xcelium* scipt to u the testbech.
Table 7.  Hadwae Desig Example File Desciptios
File Names Desciptio
Fo CPRI Multiate Desigs
<desig_example_di>/hadwae_test_desig/cpiphy_d_ed_hw.qpf Quatus® Pime poject file.
<desig_example_di>/hadwae_test_desig/cpiphy_d_ed_hw.qsf Quatus® Pime poject settigs file.
<desig_example_di>/hadwae_test_desig/cpiphy_d_ed_hw.sv Top hadwae desig file. This file istatiates the F-Tile Dyamic Recofiguatio Suite Itel FPGA IP, F-Tile Refeece ad System PLL Clocks Itel FPGA IP, ad DUT wappe.
<desig_example_di>/hadwae_test_desig/cpiphy_d_ed_dut_wappe.sv DUT wappe that istatiates DUT ad packet cliet testbech compoets.
<desig_example_di>/hadwae_test_desig/cpiphy_d_ed_hw.sdc Syopsys Desig Costaits files. You ca copy ad modify this file fo you ow Agilex™ 7 o Agilex™ 9 device.
<desig_example_di>/hadwae_test_desig/hwtest/mai_scipt.tcl Mai file fo accessig System Cosole.
<desig_example_di>/hadwae_test_desig/hwtest/sc/paamete.tcl Stoes the cofiguable vaiables of the test scipt. JTAG ID, desied dyamic ecofiguatio sequeces of the test ca be modified though the vaiables i this file.
Fo Etheet Multiate Desigs
<desig_example_di>/hadwae_test_desig/eth_f_hw.v Top hadwae desig file. This file istatiates the F-Tile Dyamic Recofiguatio Suite Itel FPGA IP, F-Tile Refeece ad System PLL Clocks Itel FPGA IP, ad DUT wappe.
<desig_example_di>/hadwae_test_desig/eth_f_hw_ip_top.sv DUT wappe that istatiates DUT ad packet cliet testbech compoets.

Fo example, ex_25G_m, ex_100G_m, o ex_400G_m.

<desig_example_di>/hadwae_test_desig/eth_f_hw.sdc Syopsys Desig Costaits files. You ca copy ad modify this file fo you ow Agilex™ 7 device o Agilex™ 9 device.
<desig_example_di>/hadwae_test_desig/hwtest/mai_scipt.tcl Mai file fo accessig System Cosole.
<desig_example_di>/hadwae_test_desig/hwtest/sc/paamete.tcl Stoes the cofiguable vaiables of the test scipt. JTAG ID, desied dyamic ecofiguatio sequeces of the test ca be modified though the vaiables i this file.
Fo PMA/FEC Diect PHY Multiate Desigs
<desig_example_di>/hadwae_test_desig/dphy_f_hw.qpf Itel Quatus Pime poject file.
<desig_example_di>/hadwae_test_desig/dphy_f_hw.qsf Itel Quatus Pime poject settigs file.
<desig_example_di>/hadwae_test_desig/dphy_f_hw.sv Top hadwae desig file. This file istatiates the F-Tile Dyamic Recofiguatio Suite Itel FPGA IP, F-Tile Refeece ad System PLL Clocks Itel FPGA IP, DUT ad Testwap compoets.
<desig_example_di>/hadwae_test_desig/dphy_f_hw.sdc Syopsys Desig Costaits files. You ca copy ad modify this file fo you ow Agilex™ 7 o Agilex™ 9 device.
<desig_example_di>/hadwae_test_desig/hwtest/mai_scipt.tcl Mai file fo accessig System Cosole.
<desig_example_di>/hadwae_test_desig/hwtest/sc/paamete.tcl Stoes the cofiguable vaiables of the test scipt. JTAG ID, desied dyamic ecofiguatio sequeces of the test ca be modified though the vaiables i this file.
Fo Etheet to CPRI Multiate Desigs
<desig_example_di>/hadwae_test_desig/eth_cpiphy_f_hw.qpf Itel Quatus Pime poject file.
<desig_example_di>/hadwae_test_desig/eth_cpiphy_f_hw.qsf Itel Quatus Pime poject settigs file.
<desig_example_di>/hadwae_test_desig/eth_cpiphy_f_hw.sv Top hadwae desig file. This file istatiates the F-Tile Dyamic Recofiguatio Suite Itel FPGA IP, F-Tile Refeece ad System PLL Clocks Itel FPGA IP, ad DUT wappe.
<desig_example_di>/hadwae_test_desig/cpiphy_f_d_hw.sv DUT wappe that istatiates F-tile CPRI PHY Multiate Itel FPGA IP
<desig_example_di>/hadwae_test_desig/eth_f_d_hw.v DUT wappe that istatiates F-tile Etheet Multiate Itel FPGA IP
<desig_example_di>/hadwae_test_desig/eth_cpiphy_f_hw.sdc Syopsys Desig Costaits file. You ca copy ad modify this file fo you ow Agilex™ 7 o Agilex™ 9 device.
<desig_example_di>/hadwae_test_desig/hwtest/mai_scipt.tcl Mai file fo accessig System Cosole.
<desig_example_di>/hadwae_test_desig/hwtest/sc/paamete.tcl Stoes the cofiguable vaiables of the test scipt. JTAG ID, desied dyamic ecofiguatio sequeces of the test ca be modified though the vaiables i this file.
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