F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench

The Etheet to CPRI Dyamic Recofiguatio example desig simulatio testbech block diagams ae show i the followig figues:
Figue 37. Simulatio Testbech Block Diagam fo Etheet to CPRI Dyamic Recofiguatio Desig Example
Figue 38. Simulatio Testbech Block Diagam fo Etheet to CPRI Dyamic Recofiguatio Desig Example (with 1GE)
Figue 39. Simulatio Testbech Block Diagam fo Etheet to CPRI Dyamic Recofiguatio Desig Example (with 1GE PTP)
The testbech pogam cotols the testbech compoets via Avalo® Memoy-Mapped Iteface access, status ad cotol sigals. The Avalo® Memoy-Mapped Iteface abite decodes the Avalo® Memoy-Mapped Iteface access fom the testbech pogam ito multiple Avalo® Memoy-Mapped Iteface slaves.
Simulatio Flow:
  • Etheet Multiate IP DUT is powe-up based o base pofile.
  • Iitialize the testbech vaiables based o powe-up pofile. The paamete settigs, located i the basic_avl_tb_top.sv file, ae:
    • DR_NUM: To idicate the umbe of dyamic ecofiguatio tasitios.
    • DR_SEQ: To idicate the dyamic ecofiguatio sequece.
  • Pefom dyamic ecofiguatio.
  • Stat taffic test.
  • Check the testbech eo flag ad detemie whethe testbech passed o failed. The eo flag is set to 1 if thee is ay eo afte dyamic ecofiguatio taffic tests.

Fo customizatio, you ca modify the DR_NUM ad DR_SEQ localpaam to cofigue the test flow. The pofile ID is passed to the dyamic ecofiguatio IP to cofigue the iteded dyamic ecofiguatio task.

Fo example, you wat to achieve this Dyamic Recofiguatio sequece: Etheet 25G-1 > CPRI 24G with RS-FEC > Etheet 10G-1.

The localpaams chages ae:
  • Localpaam DR_NUM = 2
  • Localpaam [6:0] DR_SEQ [DR_NUM-1:0] = {ETH_DR_MODE_10GE-1, CPRI_DR_MODE_24G_RSFEC};
The below RTL sippet shows the Etheet – CPRI Potocols testbech localpaams to customize: 
localpaam ETH_DR_MODE_25GE_1	 = 6'b00_00_00;
localpaam ETH_DR_MODE_10GE_1     = 6'b00_00_01;
localpaam CPRI_DR_MODE_24G_RSFEC = 6'b00_00_10;
localpaam CPRI_DR_MODE_24G  	 = 6'b00_00_11;
localpaam CPRI_DR_MODE_12G_RSFEC = 6'b00_01_00;
localpaam CPRI_DR_MODE_12G   	= 6'b00_01_01;
localpaam CPRI_DR_MODE_10G_RSFEC = 6'b00_01_10;
localpaam CPRI_DR_MODE_10G       = 6'b00_01_11;
localpaam CPRI_DR_MODE_9P8G      = 6'b00_10_00;
localpaam CPRI_DR_MODE_6G        = 6'b00_10_01;
localpaam CPRI_DR_MODE_4P9G      = 6'b00_10_10;
localpaam CPRI_DR_MODE_3G        = 6'b00_10_11;
localpaam CPRI_DR_MODE_2P4G      = 6'b00_11_00;
localpaam CPRI_DR_MODE_1G        = 6'b00_11_01;

localpaam DR_NUM = 3;
localpaam [6:0] DR_SEQ [DR_NUM-1 : 0] = {CPRI_DR_MODE_4P9G,CPRI_DR_MODE_24G_RSFEC,ETH_DR_MODE_10GE_1};

The below RTL sippet shows the Etheet – CPRI Potocols (with 1GE) testbech localpaams to customize:

localpaam ETH_DR_MODE_25GE_1      = 6'b00_00_00;
localpaam ETH_DR_MODE_10GE_1      = 6'b00_00_01;
localpaam CPRI_DR_MODE_24G_RSFEC  = 6'b00_00_10;
localpaam CPRI_DR_MODE_24G        = 6'b00_00_11;
localpaam CPRI_DR_MODE_12G_RSFEC  = 6'b00_01_00;
localpaam CPRI_DR_MODE_12G        = 6'b00_01_01;
localpaam CPRI_DR_MODE_10G_RSFEC  = 6'b00_01_10;
localpaam CPRI_DR_MODE_10G        = 6'b00_01_11;
localpaam CPRI_DR_MODE_9P8G       = 6'b00_10_00;
localpaam CPRI_DR_MODE_6G         = 6'b00_10_01;
localpaam CPRI_DR_MODE_4P9G       = 6'b00_10_10;
localpaam CPRI_DR_MODE_3G         = 6'b00_10_11;
localpaam CPRI_DR_MODE_2P4G       = 6'b00_11_00;
localpaam CPRI_DR_MODE_1G         = 6'b00_11_01;
localpaam ETH_DR_MODE_1GE_1       = 6'b00_11_10;

localpaam DR_NUM = 3;
localpaam [6:0] DR_SEQ [DR_NUM-1 : 0] = {ETH_DR_MODE_25GE_1,CPRI_DR_MODE_24G_RSFEC,ETH_DR_MODE_1GE_1};
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