F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

1.2. Generating the Design

Figue 2. Pocedue
Follow these steps to geeate a desig example:
  1. I the IP Catalog, locate ad select F-Tile Dyamic Recofiguatio Suite Itel FPGA IP. The New IP Vaiatio widow appeas.
  2. Specify a top-level ame <you_ip> fo you custom IP vaiatio. The paamete edito saves the IP vaiatio settigs i a file amed as <you_ip>.ip.
  3. O the IP tab, specify the paametes fo you IP coe vaiatio.
  4. O the Example Desig tab, ude Available Example Desig, select the Potocol ad Base Vaiat.
  5. O the Example Desig tab, ude Example Desig Files, select the Simulatio optio to geeate the testbech ad the compilatio-oly poject. Select the Sythesis optio to geeate the hadwae desig example. You must select at least oe of the Simulatio ad Sythesis optios to geeate the desig example.
  6. O the Example Desig tab, ude Geeated HDL Fomat, select Veilog HDL.
  7. O the Example Desig tab, ude Taget Developmet Kit, select the Boad.
    • If NONE is selected, the device OPN of the geeated example desig is you device selectio while ceatig the Quatus® Pime poject.
    • If Agilex™ 7 FPGA I-Seies Tasceive-SoC Developmet Kit DK-SI-AGI027FA is selected, the device OPN of the geeated example desig is AGIB027R31B1E2V. You ca expect that the VID settigs fo LTC SmatVID device ae coect.
    • If Agilex™ 7 FPGA I-Seies Tasceive-SoC Developmet Kit DK-SI-AGI027FB is selected, the device OPN of the geeated example desig is AGIB027R31B1E1VAA. You ca expect that the VID settigs fo a Epiio SmatVID device ae coect.
  8. Click the Geeate Example Desig butto. The Select Example Desig Diectoy widow appeas.

    If you wat to modify the desig example diectoy path o ame fom the default value (d_f_0_example_desig), bowse to the ew path ad type the ew desig example diectoy ame (<desig_example_di>).


Sectio Cotet
CPRI Multiate Desig Example Paametes
Etheet Multiate Desig Example Paametes
PMA/FEC Diect PHY Multiate Desig Example Paametes
Etheet to CPRI Desig Example Paametes

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