F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

1.5. Simulating the Design Example Testbench

Pocedue

Follow these steps to simulate the testbech:

  1. At the commad pompt, chage to the testbech simulatio diectoy <desig_example_di>/example_testbech. 
    cd <my_desig>/example_testbech
  2. Ru the simulatio scipt fo the suppoted simulato of you choice. The scipt compiles ad us the testbech i the simulato. Refe to the followig table Commads to Simulate the Testbech i Suppoted Simulatos.
  3. Aalyze the esults. The successful simulatio displays "Testbech Passed" o "Test Case Passed" message.
    Table 8.  Commads to Simulate the Testbech i Suppoted Simulatos
    Simulato Istuctios
    VCS* I the commad lie, type:
    sh u_vcs.sh
    Note: Dyamic Recofiguatio with AN/LT IP suppots oly VCS simulatos i desig example.
    VCS* MX I the commad lie, type:
    sh u_vcsmx.sh
    QuestaSim* I the commad lie, type:
    vsim -do u_vsim.do
    If you pefe to simulate without bigig up the GUI, type: 
    vsim -c -do u_vsim.do
    Xcelium* I the commad lie, type:
    sh u_xcelium.sh
    The followig sample output illustates a successful simulatio test u fo the CPRI multiate desig example testbech. 
    NIOS is eteig eset
NIOS is exitig eset
basic_avl_tb_top.cpiphy_d_ed_hw__tiles.z1577a_x0_y0_0.z1577a.z1577a_ist.PROTECTED: The dowsteam compoet is backpessuig by deassetig eady, but the upsteam compoet ca't be backpessued.
SIM Mode Covesio TX AM PERIOD Stadad Mode: 163832 Sim Mode:   2552
** Ifo: Cofiguig ED to CPRI 10G ....
** Ifo: Wait fo DR Ready....
** Addess offset = 0x0, ReadData  = 0x00000002
** Ifo: Statig CPRI 10G....
** Addess offset = 0x1, WiteData = 0x00000001
** Addess offset = 0x2, WiteData = 0x00008006
** Addess offset = 0x0, ReadData  = 0x00000002
** Ifo: Tigge DR iteupt
** Addess offset = 0x0, WiteData = 0x00000001
** Ifo: Wait fo DR iteupt Ack....
** Addess offset = 0x0, ReadData  = 0x00000000
** Ifo: Wait fo DR Cofig to be doe....
** Addess offset = 0x0, ReadData  = 0x00000000
** Ifo: DONE Recofigue to CPRI 10G ....
** Addess offset = 0x0, WiteData = 0x00000009
** Addess offset = 0x1, WiteData = 0x00000009
** Ifo: De-assetig eset to CPRI ....
Waitig fo TX eady
TX is eady is high at time             689130000
Waitig fo RX eady
RX is eady is high at time             709850000
*** sedig packets i pogess, waitig fo checke pass ***
** Chael 0: RX checke has eceived packets coectly!
** PASSED
** Ifo: Cofiguig ED to CPRI 9p8G ....
** Ifo: Wait fo DR Ready....
** Addess offset = 0x0, ReadData  = 0x00000002
** Ifo: Statig CPRI 9p8G....
** Addess offset = 0x1, WiteData = 0x00000006
** Addess offset = 0x2, WiteData = 0x00008007
** Addess offset = 0x0, ReadData  = 0x00000002
** Ifo: Tigge DR iteupt
** Addess offset = 0x0, WiteData = 0x00000001
** Ifo: Wait fo DR iteupt Ack....
** Addess offset = 0x0, ReadData  = 0x00000000
** Ifo: Wait fo DR Cofig to be doe....
** Addess offset = 0x0, ReadData  = 0x00000000
** Ifo: DONE Recofigue to CPRI 9p8G ....
** Addess offset = 0x0, WiteData = 0x00000006
** Addess offset = 0x1, WiteData = 0x00000006
** Ifo: De-assetig eset to CPRI ....
Waitig fo TX eady
TX is eady is high at time            1561660000
Waitig fo RX eady
RX is eady is high at time            1579800000
*** sedig packets i pogess, waitig fo checke pass ***
** Chael 0: RX checke has eceived packets coectly!
** PASSED
** Ifo: Cofiguig ED to CPRI 4p9G ....
** Ifo: Wait fo DR Ready....
** Addess offset = 0x0, ReadData  = 0x00000002
** Ifo: Statig CPRI 4p9G....
** Addess offset = 0x1, WiteData = 0x00000007
** Addess offset = 0x2, WiteData = 0x00008009
** Addess offset = 0x0, ReadData  = 0x00000002
** Ifo: Tigge DR iteupt
** Addess offset = 0x0, WiteData = 0x00000001
** Ifo: Wait fo DR iteupt Ack....
** Addess offset = 0x0, ReadData  = 0x00000000
** Ifo: Wait fo DR Cofig to be doe....
** Addess offset = 0x0, ReadData  = 0x00000000
** Ifo: DONE Recofigue to CPRI 4p9G ....
** Addess offset = 0x0, WiteData = 0x00000004
** Addess offset = 0x1, WiteData = 0x00000004
** Ifo: De-assetig eset to CPRI ....
Waitig fo TX eady
TX is eady is high at time            2415120000
Waitig fo RX eady
RX is eady is high at time            2433780000
*** sedig packets i pogess, waitig fo checke pass ***
** Chael 0: RX checke has eceived packets coectly!
** PASSED
** Ifo: Cofiguig ED to CPRI 2p4G ....
** Ifo: Wait fo DR Ready....
** Addess offset = 0x0, ReadData  = 0x00000002
** Ifo: Statig CPRI 2p4G....
** Addess offset = 0x1, WiteData = 0x00000009
** Addess offset = 0x2, WiteData = 0x0000800b
** Addess offset = 0x0, ReadData  = 0x00000002
** Ifo: Tigge DR iteupt
** Addess offset = 0x0, WiteData = 0x00000001
** Ifo: Wait fo DR iteupt Ack....
** Addess offset = 0x0, ReadData  = 0x00000000
** Ifo: Wait fo DR Cofig to be doe....
** Addess offset = 0x0, ReadData  = 0x00000000
** Ifo: DONE Recofigue to CPRI 2p4G ....
** Addess offset = 0x0, WiteData = 0x00000002
** Addess offset = 0x1, WiteData = 0x00000002
** Ifo: De-assetig eset to CPRI ....
Waitig fo TX eady
TX is eady is high at time            3269140000
Waitig fo RX eady
RX is eady is high at time            3287790000
*** sedig packets i pogess, waitig fo checke pass ***
** Chael 0: RX checke has eceived packets coectly!
** PASSED
** Ifo: Cofiguig ED to CPRI 24p3G_RSFEC ....
** Ifo: Wait fo DR Ready....
** Addess offset = 0x0, ReadData  = 0x00000002
** Ifo: Statig CPRI 24p3G_RSFEC....
** Addess offset = 0x1, WiteData = 0x0000000b
** Addess offset = 0x2, WiteData = 0x00008001
** Addess offset = 0x0, ReadData  = 0x00000002
** Ifo: Tigge DR iteupt
** Addess offset = 0x0, WiteData = 0x00000001
** Ifo: Wait fo DR iteupt Ack....
** Addess offset = 0x0, ReadData  = 0x00000000
** Ifo: Wait fo DR Cofig to be doe....
** Addess offset = 0x0, ReadData  = 0x00000000
** Ifo: DONE Recofigue to CPRI 24p3G_RSFEC ....
** Addess offset = 0x0, WiteData = 0x0000001b
** Addess offset = 0x1, WiteData = 0x0000001b
** Ifo: De-assetig eset to CPRI ....
Waitig fo TX eady
TX is eady is high at time            4158420000
Waitig fo RX eady
RX is eady is high at time            4196310000
*** sedig packets i pogess, waitig fo checke pass ***
** Chael 0: RX checke has eceived packets coectly!
** PASSED
** Testbech Completed
** Testbech Passed
$fiish called fom file "basic_avl_tb_top.sv", lie 452.
$fiish at simulatio time 4196335s
    The followig sample output illustates a successful simulatio test u fo the 100G-4 Etheet multiate dyamic ecofiguatio IP coe vaiat. 
    ---SRC IP sequece TX ch0 completed ----
---SRC IP sequece TX ch1 completed ----

---SRC IP sequece RX ch0 completed ----
---SRC IP sequece RX ch1 completed ----

---Test 50G ch 0;   ---Total 16 packets to sed ----
Cleaig coutes
-----Stat 50G pkt ge TX ----
-----Checkig 50G Packet TX/RX esult ----
---------- 16 packets Set; 0 packets Received ----
------ALL 16 packets Set out ---

---------- 16 packets Set; 16 packets Received ----
------ALL 16 packets Received ---
------50G TX/RX packet check OK ---

---Test 50G ch 1;   ---Total 32 packets to sed ----
Cleaig coutes
-----Stat 50G pkt ge TX ----
-----Checkig 50G Packet TX/RX esult ----
---------- 16 packets Set; 0 packets Received ----
---------- 32 packets Set; 32 packets Received ----
------ALL 32 packets Set out ---
------ALL 32 packets Received ---
------50G TX/RX packet check OK ---

*******************************************
** Testbech complete
** Testbech Passed
**
*******************************************
    The followig sample output illustates a successful simulatio test u fo the 50G-1 PMA/FEC Diect PHY Multiate desig example testbech. 
    ** Ifo: DONE Recofigue to PMA DIR 50G ....
####### tx_eset, x_eset deasseted ######
1.08923e+09
The time ow is 1090000s 

The time ow is 1100000s 

@1106614s: TX Ready=0, RX Ready=0, veifie_eo=0, veifie_lock =0, ux_locked =0, cd_lockedtoef =1, cd_locktodata= 0, fl_xcv_locked_dut = 0,  tx_clkout_feq_valid=0, x_clkout_feq_valid=0
The time ow is 1110000s 

@1110766s: TX Ready=0, RX Ready=0, veifie_eo=0, veifie_lock =0, ux_locked =1, cd_lockedtoef =1, cd_locktodata= 0, fl_xcv_locked_dut = 0,  tx_clkout_feq_valid=0, x_clkout_feq_valid=0
The time ow is 1120000s 

@1126396s: TX Ready=1, RX Ready=0, veifie_eo=0, veifie_lock =0, ux_locked =1, cd_lockedtoef =1, cd_locktodata= 0, fl_xcv_locked_dut = 0,  tx_clkout_feq_valid=0, x_clkout_feq_valid=0
@1127420s: TX Ready=1, RX Ready=0, veifie_eo=0, veifie_lock =0, ux_locked =1, cd_lockedtoef =1, cd_locktodata= 0, fl_xcv_locked_dut = 0,  tx_clkout_feq_valid=1, x_clkout_feq_valid=0
@1128074s: TX Ready=1, RX Ready=0, veifie_eo=0, veifie_lock =0, ux_locked =1, cd_lockedtoef =1, cd_locktodata= 1, fl_xcv_locked_dut = 1,  tx_clkout_feq_valid=1, x_clkout_feq_valid=0
The time ow is 1130000s 

The time ow is 1140000s 

@1144500s: TX Ready=1, RX Ready=1, veifie_eo=0, veifie_lock =0, ux_locked =1, cd_lockedtoef =1, cd_locktodata= 1, fl_xcv_locked_dut = 1,  tx_clkout_feq_valid=1, x_clkout_feq_valid=0
@1144815s: TX Ready=1, RX Ready=1, veifie_eo=0, veifie_lock =1, ux_locked =1, cd_lockedtoef =1, cd_locktodata= 1, fl_xcv_locked_dut = 1,  tx_clkout_feq_valid=1, x_clkout_feq_valid=0
@1145521s: TX Ready=1, RX Ready=1, veifie_eo=0, veifie_lock =1, ux_locked =1, cd_lockedtoef =1, cd_locktodata= 1, fl_xcv_locked_dut = 1,  tx_clkout_feq_valid=1, x_clkout_feq_valid=1
test_pass asseted at 1148815s

Test case passed
Oveall DR test passed
Simulatio passed

    The followig sample output illustates a successful simulatio test u fo the Etheet to CPRI desig example testbech. 

    The time ow is 630000s

The time ow is 6400000s

The time ow is 650000s

The time ow is 660000s

The time ow is 670000s

The time ow is 680000s

** Ifo: Statig CPRI4.9G cofiguatio....
** Ifo: Tigge DR iteupt
** Ifo: Wait fo DR iteupt Ack....
** Ifo: Wait fo DR Cofig to be doe....
The time ow is 690000s 

The time ow is 700000s

The time ow is 710000s

The time ow is 720000s

The time ow is 730000s

The time ow is 740000s

** Ifo: Pogam DUT soft CSR ....
The time ow is 750000s 

** Ifo: DONE Recofigue to CPRI 4.9G....
** Ifo: De-assetig eset to CPRI ....
---SRC IP sequece stated -----
Waitig fo TX eady
The time ow is 760000s 

The time ow is 770000s 

TX is eady is high at time             777412533
Waitig fo RX eady
The time ow is 780000s 

The time ow is 790000s 

RX is eady is high at time             794088533
*** sedig packets i pogess, waitig fo checke pass ***
** Chael 0: RX checke has eceived packets coectly!
** PASSED
**
*****************************************
** Testbech complete
** Testbech Passed
**
*****************************************
$fiish called fom file "basic_avl_tb_top.sv", lie 2251.
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