F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench Simulation Flow: 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench

The PMA/FEC Direct PHY Multirate example design simulation testbench block diagram is shown in the following figure:
Figure 32. Simulation Testbench Block Diagram for 50G-1 Base Variant
Figure 33. Simulation Testbench Block Diagram for 400G-8 Base Variant

The testbench program controls the testbench components via Avalon® memory-mapped interface access, status and control signals. The Avalon® memory-mapped interface arbiter decodes the Avalon® memory-mapped interface access from the testbench program into multiple Avalon® memory-mapped interface slaves.

The testwrap block internally consists of the PRBS generator and PRBS verifier. There are 2 types of testwrap blocks:
  • PMA testwrap – used in PMA direct configurations.
  • FEC testwrap – used in FEC direct configuration.
For data rates 25.7812Gbps and below in the 50G-1 base variant, the design shares a single 25G PMA testwrap.
For 50G-1 base variant design, three reference clocks (156.25MHz, 153.6MHz and 184.32MHz) are fed into the system clock:
  • Reference clock of 156.25MHz is used for Ethernet protocol data rate (i.e. 53.125G (PAM4) PMA Direct, 53.125G (PAM4) FEC Direct, 25.7812G (NRZ) PMA Direct and 10.3125G (NRZ) PMA Direct).
  • Reference clock of 153.6MHz is used for 9.8304G (NRZ) PMA Direct, 4.9152G (NRZ) PMA Direct and 2.4576G (NRZ) PMA Direct CPRI protocol data rates,
  • Reference clock of 184.32MHz is used for 24.3302G (NRZ) PMA Direct and 10.1376G (NRZ) PMA Direct CPRI protocol data rates.

For 400G-8 base variant design, one reference clock (156.25MHz) is fed into the system clock.

Simulation Flow:

  • The PMA/FEC Direct PHY Multirate IP is power-up based on base profile.
  • Initialize the testbench variables based on power-up profile. The parameter settings, located in the top_tst.sv file, are:
    • DR_NUM: To indicate the number of dynamic reconfiguration transitions.
    • DR_SEQ: To indicate the dynamic reconfiguration sequence.
  • Perform dynamic reconfiguration based on the sequence in the parameter settings.
  • Check the testbench error flag and determine whether testbench passed or failed. The error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.

For customization, you can modify the DR_NUM and DR_SEQ localparam, located in the top_tst.sv file to configure the test flow. The profile ID is passed to the IP to configure the intended dynamic reconfiguration task.

Dynamic Reconfiguration Sequence Example for 50G-1 Base Variant: 53.1G > 25.78125G > 53.1G FEC > 24.3G > 53.1G: To achieve this dynamic reconfiguration sequence, you must perform the dynamic reconfiguration transitions as shown below (four transitions) and specify the reconfiguration sequence. You update the local parameter settings file as follows: 
// Available Modes
localparam DR_MODE_50G_1      = 4'b0000; // ETH
localparam DR_MODE_25G_1      = 4'b0001; // ETH
localparam DR_MODE_24G_1      = 4'b0010; // CPRI
localparam DR_MODE_10p1G_1    = 4'b0011; // CPRI
localparam DR_MODE_9p8G_1     = 4'b0100; // CPRI
localparam DR_MODE_4p9G_1     = 4'b0101; // CPRI
localparam DR_MODE_2p4G_1     = 4'b0110; // CPRI
localparam DR_MODE_10G_1      = 4'b0111; // ETH
localparam DR_MODE_50GKP_1    = 4'b1000; // ETH

// DR from base variant (DR_MODE_50G_1) to other variants in the following order, starting from left.
localparam DR_NUM = 4;
localparam [3:0] DR_SEQ [0 : DR_NUM-1] = {DR_MODE_25G_1,DR_MODE_50GKP_1,DR_MODE_24G_1,DR_MODE_50G_1};
Dynamic Reconfiguration Sequence Example for 50G-1 Base Variant: 53.1G > 9.8G > 4.9G: To achieve this dynamic reconfiguration sequence, you must perform the dynamic reconfiguration transitions as shown below (two transitions) and specify the reconfiguration sequence. You update the local parameter settings file as follows: 
// Available Modes
localparam DR_MODE_50G_1      = 4'b0000; // ETH
localparam DR_MODE_25G_1      = 4'b0001; // ETH
localparam DR_MODE_24G_1      = 4'b0010; // CPRI
localparam DR_MODE_10p1G_1    = 4'b0011; // CPRI
localparam DR_MODE_9p8G_1     = 4'b0100; // CPRI
localparam DR_MODE_4p9G_1     = 4'b0101; // CPRI
localparam DR_MODE_2p4G_1     = 4'b0110; // CPRI
localparam DR_MODE_10G_1      = 4'b0111; // ETH
localparam DR_MODE_50GKP_1    = 4'b1000; // ETH

// DR from base variant (DR_MODE_50G_1) to other variants in the following order, starting from left.
localparam DR_NUM = 2;
localparam [3:0] DR_SEQ [0 : DR_NUM-1] = {DR_MODE_9p8G_1,DR_MODE_4p9G_1};
Dynamic Reconfiguration Sequence Example for 400G-8 Base Variant: 1x400G-8 > 2x100G-4 > 1x400G-8 > 2x200G-4: To achieve this dynamic reconfiguration sequence, you must perform the dynamic reconfiguration transitions as shown below (three transitions) and specify the reconfiguration sequence. You update the local parameter settings file as follows: 
// Available Modes
localparam DR_MODE_400G_8      = 4'b0000;
localparam DR_MODE_200G_4      = 4'b0001;
localparam DR_MODE_100G_4      = 4'b0010;

// DR from base variant (DR_MODE_400G_8) to other variants in the following order, starting from left.
localparam DR_NUM = 3;
localparam [3:0] DR_SEQ [0 : DR_NUM-1] = {DR_MODE_100G_4,DR_MODE_400G_8,DR_MODE_200G_4};
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