F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench Simulatio Flow: 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench

The PMA/FEC Diect PHY Multiate example desig simulatio testbech block diagam is show i the followig figue:
Figue 32. Simulatio Testbech Block Diagam fo 50G-1 Base Vaiat
Figue 33. Simulatio Testbech Block Diagam fo 400G-8 Base Vaiat

The testbech pogam cotols the testbech compoets via Avalo® memoy-mapped iteface access, status ad cotol sigals. The Avalo® memoy-mapped iteface abite decodes the Avalo® memoy-mapped iteface access fom the testbech pogam ito multiple Avalo® memoy-mapped iteface slaves.

The testwap block iteally cosists of the PRBS geeato ad PRBS veifie. Thee ae 2 types of testwap blocks:
  • PMA testwap – used i PMA diect cofiguatios.
  • FEC testwap – used i FEC diect cofiguatio.
Fo data ates 25.7812Gbps ad below i the 50G-1 base vaiat, the desig shaes a sigle 25G PMA testwap.
Fo 50G-1 base vaiat desig, thee efeece clocks (156.25MHz, 153.6MHz ad 184.32MHz) ae fed ito the system clock:
  • Refeece clock of 156.25MHz is used fo Etheet potocol data ate (i.e. 53.125G (PAM4) PMA Diect, 53.125G (PAM4) FEC Diect, 25.7812G (NRZ) PMA Diect ad 10.3125G (NRZ) PMA Diect).
  • Refeece clock of 153.6MHz is used fo 9.8304G (NRZ) PMA Diect, 4.9152G (NRZ) PMA Diect ad 2.4576G (NRZ) PMA Diect CPRI potocol data ates,
  • Refeece clock of 184.32MHz is used fo 24.3302G (NRZ) PMA Diect ad 10.1376G (NRZ) PMA Diect CPRI potocol data ates.

Fo 400G-8 base vaiat desig, oe efeece clock (156.25MHz) is fed ito the system clock.

Simulatio Flow:

  • The PMA/FEC Diect PHY Multiate IP is powe-up based o base pofile.
  • Iitialize the testbech vaiables based o powe-up pofile. The paamete settigs, located i the top_tst.sv file, ae:
    • DR_NUM: To idicate the umbe of dyamic ecofiguatio tasitios.
    • DR_SEQ: To idicate the dyamic ecofiguatio sequece.
  • Pefom dyamic ecofiguatio based o the sequece i the paamete settigs.
  • Check the testbech eo flag ad detemie whethe testbech passed o failed. The eo flag is set to 1 if thee is ay eo afte dyamic ecofiguatio taffic tests.

Fo customizatio, you ca modify the DR_NUM ad DR_SEQ localpaam, located i the top_tst.sv file to cofigue the test flow. The pofile ID is passed to the IP to cofigue the iteded dyamic ecofiguatio task.

Dyamic Recofiguatio Sequece Example fo 50G-1 Base Vaiat: 53.1G > 25.78125G > 53.1G FEC > 24.3G > 53.1G: To achieve this dyamic ecofiguatio sequece, you must pefom the dyamic ecofiguatio tasitios as show below (fou tasitios) ad specify the ecofiguatio sequece. You update the local paamete settigs file as follows: 
// Available Modes
localpaam DR_MODE_50G_1      = 4'b0000; // ETH
localpaam DR_MODE_25G_1      = 4'b0001; // ETH
localpaam DR_MODE_24G_1      = 4'b0010; // CPRI
localpaam DR_MODE_10p1G_1    = 4'b0011; // CPRI
localpaam DR_MODE_9p8G_1     = 4'b0100; // CPRI
localpaam DR_MODE_4p9G_1     = 4'b0101; // CPRI
localpaam DR_MODE_2p4G_1     = 4'b0110; // CPRI
localpaam DR_MODE_10G_1      = 4'b0111; // ETH
localpaam DR_MODE_50GKP_1    = 4'b1000; // ETH

// DR fom base vaiat (DR_MODE_50G_1) to othe vaiats i the followig ode, statig fom left.
localpaam DR_NUM = 4;
localpaam [3:0] DR_SEQ [0 : DR_NUM-1] = {DR_MODE_25G_1,DR_MODE_50GKP_1,DR_MODE_24G_1,DR_MODE_50G_1};
Dyamic Recofiguatio Sequece Example fo 50G-1 Base Vaiat: 53.1G > 9.8G > 4.9G: To achieve this dyamic ecofiguatio sequece, you must pefom the dyamic ecofiguatio tasitios as show below (two tasitios) ad specify the ecofiguatio sequece. You update the local paamete settigs file as follows: 
// Available Modes
localpaam DR_MODE_50G_1      = 4'b0000; // ETH
localpaam DR_MODE_25G_1      = 4'b0001; // ETH
localpaam DR_MODE_24G_1      = 4'b0010; // CPRI
localpaam DR_MODE_10p1G_1    = 4'b0011; // CPRI
localpaam DR_MODE_9p8G_1     = 4'b0100; // CPRI
localpaam DR_MODE_4p9G_1     = 4'b0101; // CPRI
localpaam DR_MODE_2p4G_1     = 4'b0110; // CPRI
localpaam DR_MODE_10G_1      = 4'b0111; // ETH
localpaam DR_MODE_50GKP_1    = 4'b1000; // ETH

// DR fom base vaiat (DR_MODE_50G_1) to othe vaiats i the followig ode, statig fom left.
localpaam DR_NUM = 2;
localpaam [3:0] DR_SEQ [0 : DR_NUM-1] = {DR_MODE_9p8G_1,DR_MODE_4p9G_1};
Dyamic Recofiguatio Sequece Example fo 400G-8 Base Vaiat: 1x400G-8 > 2x100G-4 > 1x400G-8 > 2x200G-4: To achieve this dyamic ecofiguatio sequece, you must pefom the dyamic ecofiguatio tasitios as show below (thee tasitios) ad specify the ecofiguatio sequece. You update the local paamete settigs file as follows: 
// Available Modes
localpaam DR_MODE_400G_8      = 4'b0000;
localpaam DR_MODE_200G_4      = 4'b0001;
localpaam DR_MODE_100G_4      = 4'b0010;

// DR fom base vaiat (DR_MODE_400G_8) to othe vaiats i the followig ode, statig fom left.
localpaam DR_NUM = 3;
localpaam [3:0] DR_SEQ [0 : DR_NUM-1] = {DR_MODE_100G_4,DR_MODE_400G_8,DR_MODE_200G_4};
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