F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

Documet Vesio Quatus® Pime Vesio Chages
2024.11.04 24.3 Made the followig chages:
  • Updated the desig example GUI to show Select Clock paamete i the followig sectios:
    • CPRI Multiate desig example paametes
    • Etheet Multiate Desig Example Paametes
    • PMA/FEC Diect PHY Multiate Desig Example Paametes
  • Added Select Clock paamete i the followig sectios to suppot diffeet boad ad developmet kit clock fequecies:
    • CPRI Multiate desig example paametes
    • Etheet Multiate Desig Example Paametes
    • PMA/FEC Diect PHY Multiate Desig Example Paametes
  • Added ew chapte: ANLT + DR ED Ehacemet: Use Logic alog with the followig subsectios:
    • Itefaces ad tables
    • Theoy of Opeatio
    • Usig Mai.cpp file i Use Logic
    • Use Logic Modes
    • Hadwae Testig i Susped Mode
    • Simulatio Testig i Susped Mode
  • Updated the Images i the Etheet Multiate Desig Example with AN/LT Eabled: Simulatio to show Use Logic block betwee F-Tile Auto-Negotiatio ad Lik Taiig fo Etheet Itel® FPGA IP IP ad Avalo® Memoy-Mapped Abite.
  • Updated the images to show Use Logic block i the Etheet Multiate Hadwae Desig Example with AN/LT Eabled sectio.
2024.04.11 24.1 Made the followig chages:
  • Coected the table 8 title i Simulatig the Desig Example Testbech.
  • Updated Etheet Multiate Example Desig Tab image i Etheet Multiate Desig Example Paametes.
  • Added ew paamete: Eable Auto-Negotiatio ad Lik Taiig optimized simulatio ude Auto-Negotiatio ad Lik Taiig Optios tab i Etheet Multiate Desig Example Paametes.
  • Added a ew block diagam Etheet to CPRI Dyamic Recofiguatio Hadwae Desig Example Block Diagam (25G-1 PTP with RS-FEC (with 1G PTP) i Etheet to CPRI Dyamic Recofiguatio Hadwae Desig Example.
2023.10.06 23.3 Made the followig chages:
  • Fo geeated desig examples, updated the choice of the tageted developmet kits to:
    • Agilex™ 7 I-seies Tasceive-SoC Developmet Kit DK-SI-AGI027FA
    • Agilex™ 7 FPGA I-Seies Tasceive-SoC Developmet Kit DK-SI-AGI027FB
  • Added ew paamete: Eable auto-egotiatio ad Lik Taiig i Etheet Multiate Desig Example Paametes.
  • Added ew paagaph about dyamic ecofiguatio tasitio pocess i Testig the Hadwae Desig Example.
  • Added ew topic: Etheet Multiate Desig Example: Reset Scheme i Detailed Desciptio of Etheet Multiate Desig Example.
  • Added a ew chapte: Detailed Desciptio fo Etheet Multiate Desig Example with AN/LT Eabled.
  • Added ew topic: Etheet Multiate Desig Example with AN/LT Eabled: Reset Scheme.
  • Added ew topic: PMA/FEC Diect Multiate Desig Example: Reset Scheme i Detailed Desciptio of PMA/FEC Diect Multiate Desig Example.
  • Added ew base vaiat fo the Etheet to CPRI Potocol Desig Example i Etheet to CPRI Desig Example: Fuctioal Desciptio.
    • 25G-1 PTP with RS-FEC (with 1GE PTP)
  • Added Simulatio Testbech Block Diagam fo Etheet to CPRI Dyamic Recofiguatio Desig Example (With 1GE PTP) diagam i Etheet to CPRI Dyamic Recofiguatio Desig Example: Simulatio testbech.
  • Added a ew topic: Etheet to CPRI Dyamic Recofiguatio Desig Example: Reset Scheme i Detailed Desciptio fo Etheet to CPRI Desig Example.
  • Updated the taget device list fo Taget Developmet Kit paamete i the followig sectios:
    • CPRI Multiate Desig Example Paametes
    • Etheet Multiate Desig Example Paametes
    • PMA/FEC Diect PHY Multiate Desig Example Paametes
    • Etheet to CPRI Desig Example Paametes
2023.08.17 23.2 Coected the sigal diectio fo TX ad RX seial pots fo the followig images:
  • Simulatio Testbech Block Diagam fo Etheet to CPRI Dyamic Recofiguatio Desig Example.
  • Simulatio Testbech Block Diagam fo Etheet to CPRI Dyamic Recofiguatio Desig Example (with 1GE) i Etheet to CPRI Dyamic Recofiguatio Desig Example: Simulatio Testbech.
  • Etheet to CPRI Dyamic Recofiguatio Hadwae Desig Example Block i Etheet to CPRI Dyamic Recofiguatio Hadwae Desig Example.
2023.04.03 23.1
  • Added ew base vaiat fo the Etheet to CPRI Potocol i sectio: Quick Stat Guide.
    • 25G-1 with RS-FEC with 1GE
  • Updated Etheet to CPRI Example Desig Tab image i Etheet to CPRI Desig Example Paametes.
  • Added Example Desig Files paamete value: Sythesis i Etheet to CPRI Desig Example Paametes.
  • Added ew base vaiat fo the Etheet to CPRI Potocol i sectio: Etheet to CPRI Desig Example: Fuctioal Desciptio.
  • Added ew image Simulatio Testbech Block Diagam fo Etheet to CPRI Dyamic Recofiguatio Desig Example (with 1GE).
  • Added Addess Map fo Etheet to CPRI Vaiat (with 1GE) i Etheet to CPRI Desig Example: Registes.
  • Updated the poduct family ame to "Itel Agilex 7."
2022.12.19 22.4 Added the followig:
  • Hadwae Desig Example File Desciptios fo Etheet to CPRI Multiate Desigs i Diectoy Stuctue.
  • Step 4 ote i Testig the Hadwae Desig Example.
  • Etheet Multiate Hadwae Desig Example Block Diagam fo 400GE-4 FHT Base Vaiat i Etheet Multiate Hadwae Desig Example.
  • Addess Map fo 400GE-4 FHT Base Vaiat i Etheet Multiate Desig Example: Registes.
  • PMA/FEC Diect PHY Multiate Hadwae Desig Example Block Diagam: 400G-8 Base Vaiat i PMA/FEC Diect PHY Multiate Hadwae Desig Example.
  • Updated Etheet to CPRI simulatio testbech block diagam i Etheet to CPRI Dyamic Recofiguatio Desig Example: Simulatio Testbech
  • Added Etheet to CPRI Dyamic Recofiguatio Hadwae Desig Example.
  • Added addess map fo Etheet to CPRI vaiat i Etheet to CPRI Desig Example: Registes.
2022.09.26 22.3
  • Added ew Etheet base vaiat i sectio: Quick Stat Guide.
    • FHT 400G-4 with RS-FEC
  • Added ew base vaiats fo the Etheet to CPRI Potocol i sectio: Quick Stat Guide.
    • 25G-1 RS-FEC
  • Added FHT 400G-4 base vaiat fo Etheet IP potocol.
  • Updated hadwae flow desig example steps i Etheet Multiate Hadwae Desig Example.
  • Added simulatio testbech block diagam fo 400G-4 FHT Base vaiat i Etheet Multiate Desig Example: Simulatio Testbech.
  • Added multiate hadwae desig example block diagam fo the followig PTP Base Vaiats:
    • 25GE-1 with PTP
    • 100GE-4 with PTP
    • 400GE-8 with PTP
  • Added ew topic: Etheet to CPRI Desig Example Paametes i Geeatig the Desig sectio.
  • Added Key Testbech ad Simulatio Files fo Etheet to CPRI Multiate Desigs i Diectoy Stuctue sectio.
  • Added simulatio test u esults fo the Etheet to CPRI desig example testbech i sectio Simulatig the Desig Example Testbech.
  • Updated the PMA/FEC Diect PHY Multiate Hadwae Desig Example sectio with steps fo the hadwae flow.
  • Updated the PMA/FEC Diect PHY Multiate Desig Example: Registes sectio with addess map fo 400G-8 base vaiat.
  • Added ew sectio: Detailed Desciptio fo Etheet to CPRI Potocol Dyamic Recofiguatio Desig Example.
2022.06.21 22.2
  • Updated the Suppoted Cofiguatio table i sectio: Quick Stat Guide:
    • Added ew base vaiats fo the Etheet ad PMA/FEC Diect PHY IP potocol.
      • Etheet base vaiats:
        • 100G-4 with RS-FEC ad PTP
        • 25G-1 with RS-FEC ad PTP
        • 400G-8 with RS-FEC ad PTP
      • PMA/FEC Diect PHY base vaiat: 400G-8 with RS-FEC
    • Added coespodig ew ifomatio i sectio: Detailed Desciptio fo Etheet Multiate Desig Example ad Detailed Desciptio fo PMA/FEC Diect PHY Multiate Desig Example.
  • Updated the Select Base Vaiat paamete i sectio: Etheet Multiate Desig Example Paametes.
  • Updated the followig PMA/FEC Diect PHY Multiate Desig Example Paametes:
    • Select Base Vaiat
    • Geeated File Fomat
    • Taget Developmet Kit
  • Added hadwae suppot fo 400G-8 base vaiat of the Etheet Multiate Desigs.
  • Added hadwae suppot fo 50G-1 base vaiat of the PMA/FEC Diect PHY Multiate Desigs.
    • Added ew sectio: PMA/FEC Diect PHY Multiate Hadwae Desig Example.
  • Updated the Etheet Multiate Desig Example: Registes sectio with 400G-8 base vaiat addess map.
2022.03.28 22.1
  • Updated the Suppoted Cofiguatio table i Quick Stat Guide:
    • Added ew taget vaiats fo the Etheet 100GE-1 base vaiat
    • Added 400GE-8 base vaiat fo Etheet IP potocol
    • Added 50G-1 base vaiat fo PMA/FEC diect IP potocol
  • Removed suppot fo the ModelSim* SE simulato.
  • Updated Etheet Multiate Desig Example Paametes to iclude 400G-8 base vaiat ad the dev kit suppot.
  • Updated steps i sectio: Simulatig the Desig Example Testbech.
  • Updated Diectoy Stuctue:
    • Added PMA/FEC Diect PHY-specific testbech files
    • Added Etheet-specific hadwae desig example files
  • Added ew figue: Simulatio Testbech Block Diagam fo 400GE-8 Base Vaiat
  • Added hadwae suppot fo the Etheet Multiate Desig Example.
  • Added suppot fo PMA/FEC Diect PHY Multiate desig example.
2022.01.07 21.4
  • Added suppot fo Etheet Multiate desig example.
  • Added suppot fo the Xcelium* simulato.
  • Added hadwae suppot fo the CPRI Multiate Desig Example.
  • Updated the Simulatio Testbech Block Diagam ad the customizatio istuctios i sectio: CPRI Multiate Desig Example: Simulatio Testbech.
  • Updated the addess age i sectio: CPRI Multiate Desig Example: Registes.
2021.11.17 21.3 Iitial elease.
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