F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench Dyamic Recofiguatio Sequece Example: 100GE-4 > 2x 50GE-1 > 4x 25GE-1 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench

Figue 24. Simulatio Testbech Block Diagam fo 25GE-1 Base Vaiat with AN/LT Eabled
Figue 25. Simulatio Testbech Block Diagam fo 100GE-4 Base Vaiat with AN/LT Eabled
Figue 26. Simulatio Testbech Block Diagam fo 400GE-8 Base Vaiat with AN/LT Eabled
Figue 27. Simulatio Testbech Block Diagam fo 400G-4 FHT Base Vaiat with AN/LT Eabled

The testbech pogam cotols the testbech compoets via Avalo® memoy-mapped iteface access, status ad cotol sigals. The Avalo® memoy-mapped iteface abite decodes the Avalo® memoy-mapped iteface access fom testbech pogam ito multiple Avalo® memoy-mapped iteface slaves.

Simulatio Flow:
  • Etheet Multiate IP DUT is powe-up based o base pofile.
  • Iitialize the testbech vaiables based o powe-up pofile. The paamete settigs, located i the basic_avl_tb_top.sv file, ae:
    • DR_NUM: To idicate the umbe of dyamic ecofiguatio tasitios.
    • DR_SEQ: To idicate the dyamic ecofiguatio sequece.
  • Pefom Auto-Negotiatio ad Lik Taiig.
  • Eable the Auto-Negotiatio ad Lik Taiig IP. Use logic eads AN esults ad tigges dyamic ecofiguatio flow.
  • Oce the Dyamic Recofiguatio completes, you ca pogam seq_foce_mode AN/LT CSR to otify about the Dyamic Recofigued pofile; othewise, AN/LT IP is expected to follow the AN esult.
  • Disable the AN/LT IP.
  • Move to data o Etheet mode ad stat tasmittig packets.
  • Check the testbech eo flag to detemie whethe the testbech passed o failed. The eo flag is set to 1 whe the AN/LT with Dyamic ecofiguatio ad Etheet flow is successfully completed.

Fo customizatio, you ca modify the DR_NUM ad DR_SEQ localpaam to cofigue the test flow. The pofile ID is passed to the IP to cofigue the iteded dyamic ecofiguatio task.

Dyamic Recofiguatio Sequece Example: 100GE-4 > 2x 50GE-1 > 4x 25GE-1

To achieve this dyamic ecofiguatio sequece, you must pefom two dyamic ecofiguatio tasitios ad specify the ecofiguatio sequece. You update the local paamete settigs file: 
// Available Modes
localpaam DR_MODE_1X100GE_4       = 6'b00_00_00;
localpaam DR_MODE_1X100GE_4_NOFEC = 6'b00_00_01; 
localpaam DR_MODE_1X100GE_2       = 6'b00_00_11;
localpaam DR_MODE_2x50GE_1        = 6'b01_01_00;
localpaam DR_MODE_4X25GE_1 	   = 6'b10_00_00;
localpaam DR_MODE_4X25GE_1_NOFEC  = 6'b10_00_01;

// Dyamic Recofiguatio settig
localpaam DR_NUM = 2;
localpaam [6:0] DR_SEQ [DR_NUM - 1 : 0] = {DR_MODE_4X25GE_1, DR_MODE_2X50GE_1}
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