F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled x
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description
4.1. Ethernet Multirate Design Example with AN/LT Enabled: Functional Description x
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic 4.1.2. Ethernet Multirate Design Example with AN/LT Enabled: Simulation Testbench 4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled
4.1.1. AN/LT with Dynamic Reconfiguration Design Example Enhancement: User Logic x
4.1.1.1. Interfaces 4.1.1.2. Theory of Operation 4.1.1.3. Using Main.cpp file in User Logic 4.1.1.4. User Logic Modes 4.1.1.5. Hardware Testing in Suspend Mode 4.1.1.6. Simulation Testing in Suspend Mode
4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled x
4.1.3.1. Ethernet Multirate Design Example with AN/LT Enabled: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Auto-Negotiation and Link Training Enabled
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

4.1.3. Ethernet Multirate Hardware Design Example with AN/LT Enabled

Figue 28. Etheet Multiate Hadwae Desig Example Block Diagam fo 25GE-1 Base Vaiat with AN/LT Eabled
Figue 29. Etheet Multiate Hadwae Desig Example Block Diagam fo 100GE-4 Base Vaiat with AN/LT Eabled
Figue 30. Etheet Multiate Hadwae Desig Example Block Diagam fo 400GE-8 Base Vaiat with AN/LT Eabled
Figue 31. Etheet Multiate Hadwae Desig Example Block Diagam fo 400GE-4 FHT Base Vaiat with AN/LT Eabled

I the hadwae desig example, the eset, status, ad cotol sigals fom packet cliets, F-Tile Etheet Multiate Itel® FPGA IP, ad F-Tile Dyamic Recofiguatio Suite Itel® FPGA AN/LT IP i the example desig ae coected to I-System Souces ad Pobes IPs (ISSP). The hadwae test scipts ope sevice to the ISSP to ead ad dive the values. A JTAG host is istatiated to access the Avalo® memoy-mapped itefaces.

The hadwae desig example executes the dyamic ecofiguatio tasitio pocess, check the DUT IP status, clea the MAC statistics befoe sedig 16 packets, ad lastly display the MAC statistics.

The table below summaizes the suppoted modes fo F-Tile Etheet Dyamic Recofiguatio Hadwae Example Desig fo PTP/No PTP Vaiats.
Table 18.  F-Tile Etheet Dyamic Recofiguatio Hadwae Example Desig fo PTP/No PTP Vaiats
Base Vaiat (Statup IP/Mode) Hadwae Suppot Taget Vaiats PTP mode
25G-1 Yes

25G

10G

 -
25G-1 with PTP Yes 25G PTP

10G PTP

 Advaced
100G-4 Yes 100G-4 with RS-FEC

100G-4

100G-2 RS-FEC

2×50G-1 with RS-FEC

4×25G-1 with RS-FEC

4×25G-1

 -
100G-4 with PTP Yes 100G-4 with RS-FEC ad PTP

100G-4 with PTP

100G-2 with RS-FEC ad PTP

2×50G-1 with RS-FEC ad PTP

4×25G-1 with RS-FEC ad PTP

4×25G-1 with PTP

 Basic
400G-8 Yes 400G-8 with RS-FEC

2x200G-4 with RS-FEC

4x100G-2 with RS-FEC

 -
400G-8 with PTP Yes 400G-8 with RS-FEC ad PTP

2x200G-4 with RS-FEC ad PTP

4x100G-2 RS-FEC with PTP

 Advaced
FHT 400G-4 Yes FHT 400G-4 with RS-FEC

FHT 1x200G-4 with RS-FEC

FHT 2x200G-2 with RS-FEC

FHT 2x100G-2 with RS-FEC

FHT 4x100G-1 RS-FEC

 -

Additioal Steps equied to u the PTP eabled desigs i hadwae:

The hadwae test desig cotais a hwtest subdiectoy that cotais .tcl scipts fo dyamic ecofiguatio.
  1. Fo PTP eabled desigs usig Advace Accuacy Mode (i.e. 25GE-1 with RSFEC ad PTP ad 400G-8 with RSFEC ad PTP), you must geeate the outig delay ifomatio fist befoe you u the mai_scipt.tcl.
    • Fo the steps equied to geeate this outig delay ifomatio, efe to Routig Delay Adjustmet fo Advaced Timestamp Accuacy Mode i F-tile Etheet Itel FPGA Had IP Use Guide.
    • Refe to steps 6b ad 6c i the Hadwae Desig Example of F-tile Etheet Itel FPGA Had IP Desig Example Use Guide to add the exteal module ad boad tace value.
  2. Fo PTP eabled desigs that taget the Agilex™ 7 I-Seies Tasceive-SoC Developmet Kit, the maste TOD clock is souced fom U19, OUT1. You must pogam the OUT1 clock fom the default of 166.6Mhz to the equied 125Mhz fequecy usig the developmet kit's clock cotolle GUI. Fo desigs which do ot use PTP but taget the Agilex™ 7 I-Seies Tasceive-SoC Developmet kit, the default clock settigs ae sufficiet ad this step is ot equied.
  3. A successful u displays Test <ftile_eth_d_test> Passed at System Cosole.

Fo moe ifomatio to test the desig example i hadwae, efe to Testig the Hadwae Desig Example.


Sectio Cotet
Etheet Multiate Desig Example with AN/LT Eabled: Reset Scheme

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